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picorv32
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RISC-V ISA 2.1 now calls "sbreak" officially "ebreak"

This commit is contained in:
Clifford Wolf 2016-06-06 10:46:52 +02:00
parent 490a734519
commit f4bb91b060
15 changed files with 44 additions and 44 deletions
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16
README.md
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@ -215,9 +215,9 @@ accesses.
Set this to 0 to disable the circuitry for catching illegal instructions.
The core will still trap on an `SBREAK` instruction with this option
set to 0. With IRQs enabled, an `SBREAK` normally triggers an IRQ 1. With
this option set to 0, an `SBREAK` will trap the processor without
The core will still trap on `EBREAK` instructions with this option
set to 0. With IRQs enabled, an `EBREAK` normally triggers an IRQ 1. With
this option set to 0, an `EBREAK` will trap the processor without
triggering an interrupt.
#### ENABLE_PCPI (default = 0)
@ -448,11 +448,11 @@ interrupt handler returns.
The IRQs 0-2 can be triggered internally by the following built-in interrupt sources:
| IRQ | Interrupt Source |
| ---:| -----------------------------------|
| 0 | Timer Interrupt |
| 1 | SBREAK or Illegal Instruction |
| 2 | BUS Error (Unalign Memory Access) |
| IRQ | Interrupt Source |
| ---:| ------------------------------------|
| 0 | Timer Interrupt |
| 1 | EBREAK/ECALL or Illegal Instruction |
| 2 | BUS Error (Unalign Memory Access) |
This interrupts can also be triggered by external sources, such as co-processors
connected via PCPI.

4
dhrystone/start.S
View File

@ -46,6 +46,6 @@ start:
sw a4,0(a0)
sw a5,0(a0)
/* break */
sbreak
/* trap */
ebreak

2
dhrystone/stdlib.c
View File

@ -36,7 +36,7 @@ char *malloc(int size)
// printf("[malloc(%d) -> %d (%d..%d)]", size, (int)p, heap_memory_used, heap_memory_used + size);
heap_memory_used += size;
if (heap_memory_used > 1024)
asm("sbreak");
asm("ebreak");
return p;
}

6
firmware/irq.c
View File

@ -30,7 +30,7 @@ uint32_t *irq(uint32_t *regs, uint32_t irqs)
else
print_hex(instr, 4);
print_str("\n");
__asm__ volatile ("sbreak");
__asm__ volatile ("ebreak");
}
}
@ -62,7 +62,7 @@ uint32_t *irq(uint32_t *regs, uint32_t irqs)
if ((irqs & 2) != 0) {
if (instr == 0x00100073 || instr == 0x9002) {
print_str("SBREAK instruction at 0x");
print_str("EBREAK instruction at 0x");
print_hex(pc, 8);
print_str("\n");
} else {
@ -132,7 +132,7 @@ uint32_t *irq(uint32_t *regs, uint32_t irqs)
print_dec(timer_irq_count);
print_str("\n");
__asm__ volatile ("sbreak");
__asm__ volatile ("ebreak");
}
return regs;

2
firmware/multest.c
View File

@ -75,7 +75,7 @@ void multest(void)
if (s_mul != h_mul || s_mulh != h_mulh || s_mulhsu != h_mulhsu || s_mulhu != h_mulhu) {
print_str("ERROR!\n");
__asm__ volatile ("sbreak");
__asm__ volatile ("ebreak");
return;
}

2
firmware/sieve.c
View File

@ -78,7 +78,7 @@ void sieve(void)
print_str(" OK\n");
} else {
print_str(" ERROR\n");
__asm__ volatile ("sbreak");
__asm__ volatile ("ebreak");
}
}

6
firmware/start.S
View File

@ -260,7 +260,7 @@ irq_vec:
// new irq_regs address returned from C code in a0
addi a1, zero, 0x200
beq a0, a1, 1f
sbreak
ebreak
1:
#ifdef ENABLE_FASTIRQ
@ -478,8 +478,8 @@ start:
sw a4,0(a0)
sw a5,0(a0)
/* break */
sbreak
/* trap */
ebreak
/* Hard mul functions for multest.c

30
picorv32.v
View File

@ -97,7 +97,7 @@ module picorv32 #(
output reg [31:0] eoi
);
localparam integer irq_timer = 0;
localparam integer irq_sbreak = 1;
localparam integer irq_ebreak = 1;
localparam integer irq_buserror = 2;
localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16;
@ -503,7 +503,7 @@ module picorv32 #(
reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_scall_sbreak;
reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
wire instr_trap;
@ -919,7 +919,7 @@ module picorv32 #(
instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;
instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
instr_scall_sbreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||
instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||
(COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002));
instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
@ -1273,11 +1273,11 @@ module picorv32 #(
latched_store <= pcpi_int_wr;
cpu_state <= cpu_state_fetch;
end else
if (CATCH_ILLINSN && (pcpi_timeout || instr_scall_sbreak)) begin
if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
pcpi_valid <= 0;
`debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin
next_irq_pending[irq_sbreak] = 1;
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
@ -1286,9 +1286,9 @@ module picorv32 #(
cpu_state <= cpu_state_ld_rs2;
end
end else begin
`debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin
next_irq_pending[irq_sbreak] = 1;
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
@ -1423,11 +1423,11 @@ module picorv32 #(
latched_store <= pcpi_int_wr;
cpu_state <= cpu_state_fetch;
end else
if (CATCH_ILLINSN && (pcpi_timeout || instr_scall_sbreak)) begin
if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
pcpi_valid <= 0;
`debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin
next_irq_pending[irq_sbreak] = 1;
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
@ -1574,7 +1574,7 @@ module picorv32 #(
end else
cpu_state <= cpu_state_trap;
end
if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_scall_sbreak) begin
if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin
cpu_state <= cpu_state_trap;
end

4
scripts/csmith/syscalls.c
View File

@ -44,7 +44,7 @@ void unimplemented_syscall()
const char *p = "Unimplemented system call called!\n";
while (*p)
*(volatile int*)0x10000000 = *(p++);
asm volatile ("sbreak");
asm volatile ("ebreak");
__builtin_unreachable();
}
@ -89,7 +89,7 @@ void *sbrk(ptrdiff_t incr)
void _exit(int exit_status)
{
asm volatile ("sbreak");
asm volatile ("ebreak");
__builtin_unreachable();
}

4
scripts/cxxdemo/syscalls.c
View File

@ -44,7 +44,7 @@ void unimplemented_syscall()
const char *p = "Unimplemented system call called!\n";
while (*p)
*(volatile int*)0x10000000 = *(p++);
asm volatile ("sbreak");
asm volatile ("ebreak");
__builtin_unreachable();
}
@ -89,7 +89,7 @@ void *sbrk(ptrdiff_t incr)
void _exit(int exit_status)
{
asm volatile ("sbreak");
asm volatile ("ebreak");
__builtin_unreachable();
}

2
scripts/icestorm/firmware.S
View File

@ -9,4 +9,4 @@ addi sp, sp, %lo(512)
jal ra, main
/* break */
sbreak
ebreak

2
scripts/icestorm/firmware.c
View File

@ -42,7 +42,7 @@ void gray(uint8_t c)
uint8_t gray_decoded = gray_decode(gray_simple);
if (gray_simple != gray_bitwise || gray_decoded != c)
while (1) asm volatile ("sbreak");
while (1) asm volatile ("ebreak");
output(gray_simple);
}

4
scripts/torture/riscv_test.h
View File

@ -7,7 +7,7 @@
#define RVTEST_DATA_BEGIN
#define RVTEST_DATA_END
#define RVTEST_FAIL sbreak
#define RVTEST_PASS sbreak
#define RVTEST_FAIL ebreak
#define RVTEST_PASS ebreak
#endif

2
scripts/vivado/firmware.S
View File

@ -9,4 +9,4 @@ addi sp, sp, %lo(16*1024)
jal ra, main
/* break */
sbreak
ebreak

2
tests/riscv_test.h
View File

@ -55,7 +55,7 @@ TEST_FUNC_NAME: \
sw a3,0(a0); \
sw a2,0(a0); \
sw a4,0(a0); \
sbreak;
ebreak;
#define RVTEST_CODE_END
#define RVTEST_DATA_BEGIN .balign 4;