2015-10-08 05:58:59 -04:00
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TOOLCHAIN_PREFIX = riscv32-unknown-elf-
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2015-07-19 10:09:19 -04:00
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2019-01-11 17:49:18 -05:00
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ICE40_SIM_CELLS=$(shell yosys-config --datdir/ice40/cells_sim.v)
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2019-01-11 16:14:32 -05:00
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# set to 4 for simulation
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FIRMWARE_COUNTER_BITS=18
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2015-07-19 10:09:19 -04:00
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all: example.bin
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2019-01-11 16:44:24 -05:00
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## -------------------
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## firmware generation
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2015-07-19 10:09:19 -04:00
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firmware.elf: firmware.S firmware.c firmware.lds
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2019-01-11 16:14:32 -05:00
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$(TOOLCHAIN_PREFIX)gcc \
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-DSHIFT_COUNTER_BITS=$(FIRMWARE_COUNTER_BITS) \
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-march=rv32i -Os -ffreestanding -nostdlib \
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-o $@ firmware.S firmware.c \
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2019-01-11 16:49:32 -05:00
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--std=gnu99 -Wl,-Bstatic,-T,firmware.lds,-Map,firmware.map,--strip-debug
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2019-01-11 15:20:38 -05:00
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chmod -x $@
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2015-07-19 10:09:19 -04:00
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firmware.bin: firmware.elf
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2019-01-11 15:20:38 -05:00
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$(TOOLCHAIN_PREFIX)objcopy -O binary $< $@
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chmod -x $@
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2015-07-19 10:09:19 -04:00
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firmware.hex: firmware.bin
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2019-01-11 15:20:38 -05:00
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python3 ../../firmware/makehex.py $< 128 > $@
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2015-07-19 10:09:19 -04:00
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2019-01-11 16:44:24 -05:00
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## ------------------------------
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## main flow: synth/p&r/bitstream
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2019-01-11 15:32:34 -05:00
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synth.json: example.v ../../picorv32.v firmware.hex
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yosys -v3 -l synth.log -p 'synth_ice40 -top top -json $@; write_verilog -attr2comment synth.v' $(filter %.v, $^)
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2015-07-19 10:09:19 -04:00
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2019-01-11 15:32:34 -05:00
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example.asc: synth.json example.pcf
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nextpnr-ice40 --hx8k --package ct256 --json $< --pcf example.pcf --asc $@
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2015-07-19 10:09:19 -04:00
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2016-07-14 03:07:52 -04:00
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example.bin: example.asc
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2019-01-11 15:20:38 -05:00
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icepack $< $@
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2015-07-19 10:09:19 -04:00
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2019-01-11 16:44:24 -05:00
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## -----------------
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## icarus simulation
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2019-01-11 15:20:38 -05:00
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example_tb.vvp: example.v example_tb.v ../../picorv32.v firmware.hex
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iverilog -o $@ -s testbench $(filter %.v, $^)
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chmod -x $@
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2015-07-19 10:09:19 -04:00
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2016-05-04 02:57:16 -04:00
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example_sim: example_tb.vvp
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2019-01-11 15:20:38 -05:00
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vvp -N $<
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2015-07-21 11:43:33 -04:00
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2016-05-04 02:57:16 -04:00
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example_sim_vcd: example_tb.vvp
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2019-01-11 15:20:38 -05:00
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vvp -N $< +vcd
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2015-07-21 11:43:33 -04:00
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2019-01-11 16:44:24 -05:00
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## ---------------------
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## post-synth simulation
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2019-01-11 15:32:34 -05:00
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synth_tb.vvp: example_tb.v synth.json
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2019-01-11 17:49:18 -05:00
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iverilog -o $@ -s testbench synth.v example_tb.v $(ICE40_SIM_CELLS)
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2019-01-11 15:20:38 -05:00
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chmod -x $@
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2015-07-21 11:43:33 -04:00
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2016-05-04 02:57:16 -04:00
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synth_sim: synth_tb.vvp
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2019-01-11 15:20:38 -05:00
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vvp -N $<
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2015-07-21 11:43:33 -04:00
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2016-05-04 02:57:16 -04:00
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synth_sim_vcd: synth_tb.vvp
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2019-01-11 15:20:38 -05:00
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vvp -N $< +vcd
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2015-07-21 11:43:33 -04:00
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2019-01-11 16:44:24 -05:00
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## ---------------------
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## post-route simulation
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2019-01-11 15:20:38 -05:00
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route.v: example.asc example.pcf
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icebox_vlog -L -n top -sp example.pcf $< > $@
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2015-07-21 11:43:33 -04:00
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2019-01-11 15:20:38 -05:00
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route_tb.vvp: route.v example_tb.v
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2019-01-11 17:49:18 -05:00
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iverilog -o $@ -s testbench $^ $(ICE40_SIM_CELLS)
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2019-01-11 15:20:38 -05:00
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chmod -x $@
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2015-07-21 11:43:33 -04:00
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2016-05-04 02:57:16 -04:00
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route_sim: route_tb.vvp
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2019-01-11 15:20:38 -05:00
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vvp -N $<
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2015-07-21 11:43:33 -04:00
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2016-05-04 02:57:16 -04:00
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route_sim_vcd: route_tb.vvp
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2019-01-11 15:20:38 -05:00
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vvp -N $< +vcd
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2015-07-19 10:09:19 -04:00
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2019-01-11 16:44:24 -05:00
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## ---------------------
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## miscellaneous targets
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2019-01-11 15:20:38 -05:00
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prog_sram: example.bin
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iceprog -S $<
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2015-07-19 10:09:19 -04:00
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2019-01-11 16:07:49 -05:00
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timing: example.asc example.pcf
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icetime -c 12 -tmd hx8k -P ct256 -p example.pcf -t $<
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2019-01-11 15:20:38 -05:00
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view: example.vcd
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gtkwave $< example.gtkw
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2015-07-21 11:43:33 -04:00
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2019-01-11 16:44:24 -05:00
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## ------
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## el fin
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2015-07-19 10:09:19 -04:00
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clean:
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rm -f firmware.elf firmware.map firmware.bin firmware.hex
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2019-01-11 15:32:34 -05:00
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rm -f synth.log synth.v synth.json route.v example.asc example.bin
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2016-05-04 02:57:16 -04:00
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rm -f example_tb.vvp synth_tb.vvp route_tb.vvp example.vcd
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2015-07-19 10:09:19 -04:00
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2015-07-21 11:43:33 -04:00
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.PHONY: all prog_sram view clean
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2019-01-11 16:07:49 -05:00
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.PHONY: example_sim synth_sim route_sim timing
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2015-07-21 11:43:33 -04:00
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.PHONY: example_sim_vcd synth_sim_vcd route_sim_vcd
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