picorv32/scripts/vivado/synth_speed.tcl


read_verilog ../../picorv32.v
read_xdc synth_speed.xdc

synth_design -part xc7k70t-fbg676 -top picorv32_axi
opt_design
place_design
route_design

report_utilization
report_timing

write_verilog -force synth_speed.v
Makefile for Vivado scripts 2015-06-09 06:45:45 -04:00
			`read_verilog ../../picorv32.v`
			`read_xdc synth_speed.xdc`

Updated vivado scripts 2015-06-26 17:41:13 -04:00			`synth_design -part xc7k70t-fbg676 -top picorv32_axi`
Makefile for Vivado scripts 2015-06-09 06:45:45 -04:00			`opt_design`
			`place_design`
			`route_design`

			`report_utilization`
			`report_timing`

			`write_verilog -force synth_speed.v`