mirror of https://github.com/YosysHQ/picorv32.git
Updated vivado scripts
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@ -2,13 +2,11 @@
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read_verilog ../../picorv32.v
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read_xdc synth_area.xdc
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synth_design -part xc7a15t-fgg484 -top picorv32_axi
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synth_design -part xc7k70t-fbg676 -top picorv32_axi
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opt_design
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place_design
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route_design
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report_utilization
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report_timing
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# report_timing
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write_verilog -force synth_area.v
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@ -2,7 +2,7 @@
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read_verilog ../../picorv32.v
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read_xdc synth_speed.xdc
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synth_design -part xc7a15t-fgg484 -top picorv32_axi
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synth_design -part xc7k70t-fbg676 -top picorv32_axi
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opt_design
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place_design
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route_design
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@ -1 +1 @@
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create_clock -period 4.00 [get_ports clk]
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create_clock -period 2.50 [get_ports clk]
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