picorv32/scripts/vivado/synth_area_regular.tcl

read_verilog ../../picorv32.v
read_verilog synth_area_top.v
read_xdc synth_area.xdc

synth_design -part xc7k70t-fbg676 -top top_regular
opt_design -resynth_seq_area

report_utilization
report_timing
Added vivado synth_area_{small,regular,large}.tcl scripts 2015-07-01 15:51:15 -04:00			`read_verilog ../../picorv32.v`
			`read_verilog synth_area_top.v`
			`read_xdc synth_area.xdc`

Vivado 2015.2 area evaluation 2015-07-01 16:18:20 -04:00			`synth_design -part xc7k70t-fbg676 -top top_regular`
Added vivado synth_area_{small,regular,large}.tcl scripts 2015-07-01 15:51:15 -04:00			`opt_design -resynth_seq_area`

			`report_utilization`
Enabled report_timing in vivado synth_area scripts 2015-07-08 04:16:10 -04:00			`report_timing`