mirror of https://github.com/YosysHQ/picorv32.git
Fix tabs
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@ -13,7 +13,7 @@ module testbench;
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end
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wire mem_valid;
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reg mem_valid_q;
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reg mem_valid_q;
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wire mem_instr;
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reg mem_ready;
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wire [31:0] mem_addr;
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@ -49,43 +49,43 @@ module testbench;
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initial $readmemh("dhry.hex", memory);
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always @(posedge clk) begin
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mem_ready <= 1'b0;
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mem_ready <= 1'b0;
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mem_rdata[ 7: 0] <= 'bx;
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mem_rdata[15: 8] <= 'bx;
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mem_rdata[23:16] <= 'bx;
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mem_rdata[31:24] <= 'bx;
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mem_rdata[ 7: 0] <= 'bx;
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mem_rdata[15: 8] <= 'bx;
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mem_rdata[23:16] <= 'bx;
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mem_rdata[31:24] <= 'bx;
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if (mem_valid & !mem_valid_q) begin
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if (|mem_wstrb) begin
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mem_ready <= 1'b1;
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if (|mem_wstrb) begin
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mem_ready <= 1'b1;
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case (mem_addr)
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32'h1000_0000: begin
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case (mem_addr)
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32'h1000_0000: begin
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`ifndef TIMING
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$write("%c", mem_wdata);
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$fflush();
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$write("%c", mem_wdata);
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$fflush();
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`endif
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end
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default: begin
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if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24];
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end
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endcase
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end
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else begin
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mem_ready <= 1'b1;
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end
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default: begin
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if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24];
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end
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endcase
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end
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else begin
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mem_ready <= 1'b1;
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mem_rdata[ 7: 0] <= memory[mem_addr + 0];
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mem_rdata[15: 8] <= memory[mem_addr + 1];
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mem_rdata[23:16] <= memory[mem_addr + 2];
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mem_rdata[31:24] <= memory[mem_addr + 3];
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end
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mem_rdata[ 7: 0] <= memory[mem_addr + 0];
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mem_rdata[15: 8] <= memory[mem_addr + 1];
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mem_rdata[23:16] <= memory[mem_addr + 2];
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mem_rdata[31:24] <= memory[mem_addr + 3];
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end
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end
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mem_valid_q <= mem_valid;
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mem_valid_q <= mem_valid;
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end
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initial begin
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