mirror of https://github.com/YosysHQ/picorv32.git
testbench_slow_mem
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0906b1b4b4
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c0d1c55106
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@ -13,6 +13,9 @@ endif
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test: testbench.vvp dhry.hex
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vvp -N testbench.vvp
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test_slow_mem: testbench_slow_mem.vvp dhry.hex
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vvp -N testbench_slow_mem.vvp
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timing: timing.txt
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grep '^##' timing.txt | gawk 'x != "" {print x,$$3-y;} {x=$$2;y=$$3;}' | sort | uniq -c | \
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gawk '{printf("%03d-%-7s %2d %-8s (%d)\n",$$3,$$2,$$3,$$2,$$1);}' | sort | cut -c13-
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@ -24,6 +27,10 @@ testbench.vvp: testbench.v ../picorv32.v
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iverilog -o testbench.vvp testbench.v ../picorv32.v
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chmod -x testbench.vvp
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testbench_slow_mem.vvp: testbench_slow_mem.v ../picorv32.v
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iverilog -o testbench_slow_mem.vvp testbench_slow_mem.v ../picorv32.v
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chmod -x testbench_slow_mem.vvp
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timing.vvp: testbench.v ../picorv32.v
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iverilog -o timing.vvp -DTIMING testbench.v ../picorv32.v
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chmod -x timing.vvp
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@ -50,7 +57,7 @@ endif
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dhry_1.o dhry_2.o: CFLAGS += -Wno-implicit-int -Wno-implicit-function-declaration
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clean:
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rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.vvp testbench.vcd timing.vvp timing.txt
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rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.vvp testbench.vcd timing.vvp timing.txt testbench_slow_mem.vvp
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.PHONY: test clean
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@ -0,0 +1,114 @@
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`timescale 1 ns / 1 ps
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module testbench;
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reg clk = 1;
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reg resetn = 0;
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wire trap;
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always #5 clk = ~clk;
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initial begin
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repeat (100) @(posedge clk);
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resetn <= 1;
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end
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wire mem_valid;
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reg mem_valid_q;
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wire mem_instr;
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reg mem_ready;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [3:0] mem_wstrb;
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reg [31:0] mem_rdata;
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picorv32 #(
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.BARREL_SHIFTER(1),
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.ENABLE_FAST_MUL(1),
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.ENABLE_DIV(1),
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.PROGADDR_RESET('h10000),
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.STACKADDR('h10000)
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) uut (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata ),
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.mem_la_read (),
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.mem_la_write(),
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.mem_la_addr (),
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.mem_la_wdata(),
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.mem_la_wstrb()
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);
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reg [7:0] memory [0:256*1024-1];
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initial $readmemh("dhry.hex", memory);
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always @(posedge clk) begin
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mem_ready <= 1'b0;
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mem_rdata[ 7: 0] <= 'bx;
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mem_rdata[15: 8] <= 'bx;
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mem_rdata[23:16] <= 'bx;
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mem_rdata[31:24] <= 'bx;
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if (mem_valid & !mem_valid_q) begin
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if (|mem_wstrb) begin
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mem_ready <= 1'b1;
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case (mem_addr)
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32'h1000_0000: begin
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`ifndef TIMING
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$write("%c", mem_wdata);
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$fflush();
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`endif
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end
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default: begin
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if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24];
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end
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endcase
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end
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else begin
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mem_ready <= 1'b1;
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mem_rdata[ 7: 0] <= memory[mem_addr + 0];
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mem_rdata[15: 8] <= memory[mem_addr + 1];
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mem_rdata[23:16] <= memory[mem_addr + 2];
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mem_rdata[31:24] <= memory[mem_addr + 3];
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end
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end
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mem_valid_q <= mem_valid;
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end
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initial begin
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$dumpfile("testbench.vcd");
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$dumpvars(0, testbench);
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end
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always @(posedge clk) begin
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if (resetn && trap) begin
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repeat (10) @(posedge clk);
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$display("TRAP");
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$finish;
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end
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end
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`ifdef TIMING
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initial begin
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repeat (100000) @(posedge clk);
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$finish;
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end
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always @(posedge clk) begin
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if (uut.dbg_next)
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$display("## %-s %d", uut.dbg_ascii_instr ? uut.dbg_ascii_instr : "pcpi", uut.count_cycle);
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end
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`endif
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endmodule
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