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Fix tabs

This commit is contained in:
Tom Verbeure 2016-09-03 08:30:16 -07:00
parent c0d1c55106
commit 029b72fecc
1 changed files with 29 additions and 29 deletions
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58
dhrystone/testbench_slow_mem.v
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@ -13,7 +13,7 @@ module testbench;
end end
wire mem_valid; wire mem_valid;
reg mem_valid_q; reg mem_valid_q;
wire mem_instr; wire mem_instr;
reg mem_ready; reg mem_ready;
wire [31:0] mem_addr; wire [31:0] mem_addr;
@ -49,43 +49,43 @@ module testbench;
initial $readmemh("dhry.hex", memory); initial $readmemh("dhry.hex", memory);
always @(posedge clk) begin always @(posedge clk) begin
mem_ready <= 1'b0; mem_ready <= 1'b0;
mem_rdata[ 7: 0] <= 'bx; mem_rdata[ 7: 0] <= 'bx;
mem_rdata[15: 8] <= 'bx; mem_rdata[15: 8] <= 'bx;
mem_rdata[23:16] <= 'bx; mem_rdata[23:16] <= 'bx;
mem_rdata[31:24] <= 'bx; mem_rdata[31:24] <= 'bx;
if (mem_valid & !mem_valid_q) begin if (mem_valid & !mem_valid_q) begin
if (|mem_wstrb) begin if (|mem_wstrb) begin
mem_ready <= 1'b1; mem_ready <= 1'b1;
case (mem_addr) case (mem_addr)
32'h1000_0000: begin 32'h1000_0000: begin
`ifndef TIMING `ifndef TIMING
$write("%c", mem_wdata); $write("%c", mem_wdata);
$fflush(); $fflush();
`endif `endif
end end
default: begin default: begin
if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0]; if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8]; if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8];
if (mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16]; if (mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16];
if (mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24]; if (mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24];
end end
endcase endcase
end end
else begin else begin
mem_ready <= 1'b1; mem_ready <= 1'b1;
mem_rdata[ 7: 0] <= memory[mem_addr + 0]; mem_rdata[ 7: 0] <= memory[mem_addr + 0];
mem_rdata[15: 8] <= memory[mem_addr + 1]; mem_rdata[15: 8] <= memory[mem_addr + 1];
mem_rdata[23:16] <= memory[mem_addr + 2]; mem_rdata[23:16] <= memory[mem_addr + 2];
mem_rdata[31:24] <= memory[mem_addr + 3]; mem_rdata[31:24] <= memory[mem_addr + 3];
end end
end end
mem_valid_q <= mem_valid; mem_valid_q <= mem_valid;
end end
initial begin initial begin