mirror of https://github.com/YosysHQ/picorv32.git
Added PCPI to picorv32_axi
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picorv32.v
85
picorv32.v
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@ -1072,6 +1072,7 @@ module picorv32_axi #(
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parameter [ 0:0] ENABLE_COUNTERS = 1,
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parameter [ 0:0] ENABLE_REGS_16_31 = 1,
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parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
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parameter [ 0:0] ENABLE_PCPI = 0,
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parameter [ 0:0] ENABLE_MUL = 0,
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parameter [ 0:0] ENABLE_IRQ = 0,
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parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
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@ -1105,6 +1106,18 @@ module picorv32_axi #(
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output mem_axi_rready,
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input [31:0] mem_axi_rdata,
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// Pico Co-Processor Interface (PCPI)
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output pcpi_insn_valid,
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output [31:0] pcpi_insn,
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output pcpi_rs1_valid,
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output [31:0] pcpi_rs1,
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output pcpi_rs2_valid,
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output [31:0] pcpi_rs2,
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input pcpi_rd_valid,
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input [31:0] pcpi_rd,
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input pcpi_wait,
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input pcpi_ready,
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// IRQ interface
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input [31:0] irq,
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output [31:0] eoi
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@ -1117,16 +1130,15 @@ module picorv32_axi #(
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wire mem_ready;
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wire [31:0] mem_rdata;
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wire pcpi_insn_valid;
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wire [31:0] pcpi_insn;
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wire pcpi_rs1_valid;
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wire [31:0] pcpi_rs1;
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wire pcpi_rs2_valid;
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wire [31:0] pcpi_rs2;
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wire pcpi_rd_valid;
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wire [31:0] pcpi_rd;
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wire pcpi_wait;
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wire pcpi_ready;
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wire mul_pcpi_wait;
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wire mul_pcpi_ready;
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wire mul_pcpi_rd_valid;
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wire [31:0] mul_pcpi_rd;
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wire int_pcpi_wait = mul_pcpi_wait || (pcpi_wait && ENABLE_PCPI);
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wire int_pcpi_ready = mul_pcpi_ready || (pcpi_ready && ENABLE_PCPI);
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wire int_pcpi_rd_valid = mul_pcpi_rd_valid || (pcpi_rd_valid && ENABLE_PCPI);
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wire [31:0] int_pcpi_rd = mul_pcpi_rd_valid ? mul_pcpi_rd : pcpi_rd;
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picorv32_axi_adapter axi_adapter (
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.clk (clk ),
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@ -1159,30 +1171,31 @@ module picorv32_axi #(
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generate if (ENABLE_MUL) begin
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picorv32_pcpi_mul pcpi_mul (
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.clk (clk ),
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.resetn (resetn ),
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.pcpi_insn_valid(pcpi_insn_valid),
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.pcpi_insn (pcpi_insn ),
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.pcpi_rs1_valid (pcpi_rs1_valid ),
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.pcpi_rs1 (pcpi_rs1 ),
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.pcpi_rs2_valid (pcpi_rs2_valid ),
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.pcpi_rs2 (pcpi_rs2 ),
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.pcpi_rd_valid (pcpi_rd_valid ),
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.pcpi_rd (pcpi_rd ),
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.pcpi_wait (pcpi_wait ),
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.pcpi_ready (pcpi_ready )
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.clk (clk ),
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.resetn (resetn ),
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.pcpi_insn_valid( pcpi_insn_valid),
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.pcpi_insn ( pcpi_insn ),
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.pcpi_rs1_valid ( pcpi_rs1_valid ),
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.pcpi_rs1 ( pcpi_rs1 ),
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.pcpi_rs2_valid ( pcpi_rs2_valid ),
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.pcpi_rs2 ( pcpi_rs2 ),
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.pcpi_rd_valid (mul_pcpi_rd_valid ),
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.pcpi_rd (mul_pcpi_rd ),
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.pcpi_wait (mul_pcpi_wait ),
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.pcpi_ready (mul_pcpi_ready )
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);
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end else begin
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assign pcpi_rd = 1'bx;
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assign pcpi_wait = 0;
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assign pcpi_ready = 0;
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assign mul_pcpi_rd_valid = 0;
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assign mul_pcpi_rd = 1'bx;
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assign mul_pcpi_wait = 0;
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assign mul_pcpi_ready = 0;
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end endgenerate
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picorv32 #(
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.ENABLE_COUNTERS (ENABLE_COUNTERS ),
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.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
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.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
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.ENABLE_PCPI (ENABLE_MUL ),
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.ENABLE_PCPI (ENABLE_PCPI || ENABLE_MUL),
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.ENABLE_IRQ (ENABLE_IRQ ),
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.MASKED_IRQ (MASKED_IRQ ),
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.PROGADDR_RESET (PROGADDR_RESET ),
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@ -1200,16 +1213,16 @@ module picorv32_axi #(
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.mem_ready(mem_ready),
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.mem_rdata(mem_rdata),
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.pcpi_insn_valid(pcpi_insn_valid),
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.pcpi_insn (pcpi_insn ),
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.pcpi_rs1_valid (pcpi_rs1_valid ),
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.pcpi_rs1 (pcpi_rs1 ),
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.pcpi_rs2_valid (pcpi_rs2_valid ),
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.pcpi_rs2 (pcpi_rs2 ),
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.pcpi_rd_valid (pcpi_rd_valid ),
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.pcpi_rd (pcpi_rd ),
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.pcpi_wait (pcpi_wait ),
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.pcpi_ready (pcpi_ready ),
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.pcpi_insn_valid( pcpi_insn_valid),
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.pcpi_insn ( pcpi_insn ),
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.pcpi_rs1_valid ( pcpi_rs1_valid ),
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.pcpi_rs1 ( pcpi_rs1 ),
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.pcpi_rs2_valid ( pcpi_rs2_valid ),
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.pcpi_rs2 ( pcpi_rs2 ),
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.pcpi_rd_valid (int_pcpi_rd_valid ),
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.pcpi_rd (int_pcpi_rd ),
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.pcpi_wait (int_pcpi_wait ),
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.pcpi_ready (int_pcpi_ready ),
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.irq(irq),
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.eoi(eoi)
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