mirror of https://github.com/YosysHQ/picorv32.git
Implemented picorv32_pcpi_mul
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picorv32.v
66
picorv32.v
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@ -985,13 +985,17 @@ module picorv32_pcpi_mul (
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wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
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wire instr_rs2_signed = |{instr_mulh};
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reg pcpi_wait_q;
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wire mul_start = pcpi_wait && !pcpi_wait_q;
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always @(posedge clk) begin
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instr_mul <= 0;
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instr_mulh <= 0;
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instr_mulhsu <= 0;
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instr_mulhu <= 0;
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if (pcpi_insn_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
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if (resetn && pcpi_insn_valid && pcpi_rs1_valid && pcpi_rs2_valid &&
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pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
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case (pcpi_insn[14:12])
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3'b000: instr_mul <= 1;
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3'b001: instr_mulh <= 1;
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@ -1001,26 +1005,58 @@ module picorv32_pcpi_mul (
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end
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pcpi_wait <= instr_any_mul;
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pcpi_wait_q <= pcpi_wait;
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end
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// FIXME: This is just a behavioral model
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reg [63:0] rs1, rs2, rd, rdx;
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reg [6:0] mul_counter;
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reg mul_waiting;
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reg mul_finish;
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always @(posedge clk) begin
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mul_finish <= 0;
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if (!resetn) begin
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mul_waiting <= 1;
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end else
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if (mul_waiting) begin
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if (instr_rs1_signed)
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rs1 <= $signed(pcpi_rs1);
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else
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rs1 <= $unsigned(pcpi_rs1);
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if (instr_rs2_signed)
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rs2 <= $signed(pcpi_rs2);
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else
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rs2 <= $unsigned(pcpi_rs2);
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rd <= 0;
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rdx <= 0;
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mul_counter <= instr_any_mulh ? 64 : 32;
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mul_waiting <= !mul_start;
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end else begin
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// carry save accumulator
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if (rs1[0]) begin
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rd <= rd ^ rdx ^ rs2;
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rdx <= ((rd & rdx) | (rd & rs2) | (rdx & rs2)) << 1;
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end else begin
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rd <= rd ^ rdx;
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rdx <= (rd & rdx) << 1;
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end
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rs1 <= rs1 >> 1;
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rs2 <= rs2 << 1;
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mul_counter <= mul_counter - 1;
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if (!mul_counter) begin
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mul_finish <= 1;
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mul_waiting <= 1;
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end
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end
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end
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reg [63:0] rs1, rs2;
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always @(posedge clk) begin
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pcpi_rd_valid <= 0;
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pcpi_ready <= 0;
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if (pcpi_rs1_valid && pcpi_rs2_valid && instr_any_mul) begin
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if (instr_rs1_signed)
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rs1 = $signed(pcpi_rs1);
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else
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rs1 = $unsigned(pcpi_rs1);
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if (instr_rs2_signed)
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rs2 = $signed(pcpi_rs2);
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else
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rs2 = $unsigned(pcpi_rs2);
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pcpi_rd <= instr_any_mulh ? (rs1 * rs2) >> 32 : rs1 * rs2;
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if (mul_finish) begin
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pcpi_rd <= instr_any_mulh ? rd >> 32 : rd;
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pcpi_rd_valid <= 1;
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pcpi_ready <= 1;
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end
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