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Minor README changes
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@ -14,7 +14,7 @@ Features and Typical Applications:
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----------------------------------
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- Small (~1000 LUTs in a 7-Series Xilinx FGPA)
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- High fMAX (>250 MHz on 7-Series Xilinx FGPAs)
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- High fMAX (~250 MHz on 7-Series Xilinx FGPAs)
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- Selectable native memory interface or AXI4-Lite master
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This CPU is meant to be used as auxiliary processor in FPGA designs and ASICs. Due
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@ -154,7 +154,7 @@ The IRQs 0-2 can be triggered internally and have the following meaning:
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The core has 4 additional 32-bit registers `q0 .. q3` that are used for IRQ
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handling. When an IRQ triggers, the register `q0` contains the return address
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and `q1` contains a bitmask of all active IRQs. I.e. one call to the interrupt
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and `q1` contains a bitmask of all active IRQs. This means one call to the interrupt
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handler might need to service one than more IRQ when more than one bit is set
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in `q1`.
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