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picorv32_pcpi_div: Compactify logic
- select between quotient and divident, before negating (saves one negating path) - generate a single-bit finish-flag from quotient mask
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1 changed files with 8 additions and 5 deletions
13
picorv32.v
13
picorv32.v
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@ -2455,6 +2455,8 @@ module picorv32_pcpi_div (
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reg [31:0] quotient_msk;
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reg running;
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reg outsign;
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reg finished;
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wire[31:0] out = (instr_div || instr_divu) ? quotient : dividend;
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always @(posedge clk) begin
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pcpi_ready <= 0;
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@ -2466,13 +2468,14 @@ module picorv32_pcpi_div (
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end else
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if (start) begin
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running <= 1;
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finished <= 0;
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dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;
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divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
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outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);
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quotient <= 0;
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quotient_msk <= 1 << 31;
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end else
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if (!quotient_msk && running) begin
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if (finished && running) begin
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running <= 0;
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pcpi_ready <= 1;
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pcpi_wr <= 1;
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@ -2484,10 +2487,8 @@ module picorv32_pcpi_div (
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instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h3138d0e1;
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endcase
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`else
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if (instr_div || instr_divu)
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pcpi_rd <= outsign ? -quotient : quotient;
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else
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pcpi_rd <= outsign ? -dividend : dividend;
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pcpi_rd <= outsign ? -out : out;
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`endif
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end else begin
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if (divisor <= dividend) begin
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@ -2496,8 +2497,10 @@ module picorv32_pcpi_div (
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end
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divisor <= divisor >> 1;
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`ifdef RISCV_FORMAL_ALTOPS
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finished <= quotient_msk[1];
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quotient_msk <= quotient_msk >> 5;
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`else
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finished <= quotient_msk[0];
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quotient_msk <= quotient_msk >> 1;
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`endif
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end
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