mirror of https://github.com/YosysHQ/picorv32.git
Added CATCH_MISALIGN and CATCH_ILLINSN
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@ -158,6 +158,15 @@ latches the value internally.
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This parameter is only available for the `picorv32` core. In the
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`picorv32_axi` core this is implicitly set to 0.
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#### CATCH_MISALIGN (default = 1)
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Set this to 0 to disable the circuitry for catching misaligned memory
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accesses.
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#### CATCH_ILLINSN (default = 1)
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Set this to 0 to disable the circuitry for catching illegal instructions.
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#### ENABLE_PCPI (default = 0)
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Set this to 1 to enable the Pico Co-Processor Interface (PCPI).
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22
picorv32.v
22
picorv32.v
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@ -30,6 +30,8 @@ module picorv32 #(
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parameter [ 0:0] ENABLE_REGS_16_31 = 1,
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parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
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parameter [ 0:0] LATCHED_MEM_RDATA = 0,
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parameter [ 0:0] CATCH_MISALIGN = 1,
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parameter [ 0:0] CATCH_ILLINSN = 1,
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parameter [ 0:0] ENABLE_PCPI = 0,
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parameter [ 0:0] ENABLE_MUL = 0,
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parameter [ 0:0] ENABLE_IRQ = 0,
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@ -280,7 +282,7 @@ module picorv32 #(
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reg is_alu_reg_reg;
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reg is_compare;
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assign instr_trap = !{instr_lui, instr_auipc, instr_jal, instr_jalr,
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assign instr_trap = (CATCH_ILLINSN || ENABLE_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr,
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instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu,
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instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
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instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
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@ -569,8 +571,8 @@ module picorv32 #(
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reg_alu_out <= alu_out;
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if (WITH_PCPI) begin
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if (pcpi_valid && !pcpi_int_wait) begin
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if (WITH_PCPI && CATCH_ILLINSN) begin
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if (resetn && pcpi_valid && !pcpi_int_wait) begin
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if (pcpi_timeout_counter)
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pcpi_timeout_counter <= pcpi_timeout_counter - 1;
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end else
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@ -710,7 +712,7 @@ module picorv32 #(
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`ifdef DEBUG
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$display("DECODE: 0x%08x %-0s", reg_pc, instruction ? instruction : "UNKNOWN");
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`endif
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if (instr_trap) begin
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if ((CATCH_ILLINSN || WITH_PCPI) && instr_trap) begin
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if (WITH_PCPI) begin
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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if (ENABLE_REGS_DUALPORT) begin
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@ -724,7 +726,7 @@ module picorv32 #(
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latched_store <= pcpi_int_wr;
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cpu_state <= cpu_state_fetch;
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end else
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if (pcpi_timeout) begin
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if (CATCH_ILLINSN && pcpi_timeout) begin
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`ifdef DEBUG
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$display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);
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`endif
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@ -848,7 +850,7 @@ module picorv32 #(
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latched_store <= pcpi_int_wr;
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cpu_state <= cpu_state_fetch;
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end else
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if (pcpi_timeout) begin
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if (CATCH_ILLINSN && pcpi_timeout) begin
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`ifdef DEBUG
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$display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);
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`endif
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@ -962,7 +964,7 @@ module picorv32 #(
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end
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endcase
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if (resetn && (mem_do_rdata || mem_do_wdata)) begin
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if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
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if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
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`ifdef DEBUG
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$display("MISALIGNED WORD: 0x%08x", reg_op1);
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@ -982,7 +984,7 @@ module picorv32 #(
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cpu_state <= cpu_state_trap;
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end
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end
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if (resetn && mem_do_rinst && reg_pc[1:0] != 0) begin
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if (CATCH_MISALIGN && resetn && mem_do_rinst && reg_pc[1:0] != 0) begin
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`ifdef DEBUG
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$display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);
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`endif
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@ -1149,6 +1151,8 @@ module picorv32_axi #(
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parameter [ 0:0] ENABLE_COUNTERS = 1,
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parameter [ 0:0] ENABLE_REGS_16_31 = 1,
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parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
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parameter [ 0:0] CATCH_MISALIGN = 1,
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parameter [ 0:0] CATCH_ILLINSN = 1,
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parameter [ 0:0] ENABLE_PCPI = 0,
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parameter [ 0:0] ENABLE_MUL = 0,
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parameter [ 0:0] ENABLE_IRQ = 0,
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@ -1241,6 +1245,8 @@ module picorv32_axi #(
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.ENABLE_COUNTERS (ENABLE_COUNTERS ),
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.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
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.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
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.CATCH_MISALIGN (CATCH_MISALIGN ),
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.CATCH_ILLINSN (CATCH_ILLINSN ),
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.ENABLE_PCPI (ENABLE_PCPI ),
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.ENABLE_MUL (ENABLE_MUL ),
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.ENABLE_IRQ (ENABLE_IRQ ),
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