mirror of https://github.com/YosysHQ/picorv32.git
Add rvfi_halt and rvfi_intr ports
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@ -112,6 +112,8 @@ module picorv32 #(
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output reg [ 7:0] rvfi_order,
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output reg [ 7:0] rvfi_order,
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output reg [31:0] rvfi_insn,
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output reg [31:0] rvfi_insn,
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output reg rvfi_trap,
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output reg rvfi_trap,
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output reg rvfi_halt,
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output reg rvfi_intr,
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output reg [ 4:0] rvfi_rs1_addr,
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output reg [ 4:0] rvfi_rs1_addr,
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output reg [ 4:0] rvfi_rs2_addr,
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output reg [ 4:0] rvfi_rs2_addr,
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output reg [31:0] rvfi_rs1_rdata,
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output reg [31:0] rvfi_rs1_rdata,
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@ -1912,6 +1914,8 @@ module picorv32 #(
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rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;
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rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;
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rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
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rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
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rvfi_trap <= trap;
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rvfi_trap <= trap;
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rvfi_halt <= trap;
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rvfi_intr <= 0;
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if (!resetn) begin
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if (!resetn) begin
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rvfi_rd_addr <= 0;
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rvfi_rd_addr <= 0;
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