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picorv32
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Update picorv32.v 

Clocked process for the AXI_BREADY signal.
This commit is contained in:
Sebastian Zanker 2020-12-16 09:00:03 +01:00
parent f9b1beb4cf
commit 727f2fbfbb
1 changed files with 15 additions and 2 deletions
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17
picorv32.v
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@ -2764,6 +2764,8 @@ module picorv32_axi_adapter (
reg ack_arvalid;
reg ack_wvalid;
reg xfer_done;
reg axi_bready;
assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid;
assign mem_axi_awaddr = mem_addr;
@ -2778,9 +2780,21 @@ module picorv32_axi_adapter (
assign mem_axi_wstrb = mem_wstrb;
assign mem_ready = mem_axi_bvalid || mem_axi_rvalid;
assign mem_axi_bready = mem_valid && |mem_wstrb;
//assign mem_axi_bready = mem_valid && |mem_wstrb;
assign mem_axi_rready = mem_valid && !mem_wstrb;
assign mem_rdata = mem_axi_rdata;
// control logic for AXI_BREADY
always @(posedge clk) begin : AXI_BREADY_p
axi_bready <= 1'b0;
if (mem_axi_bvalid && mem_valid && |mem_wstrb && ~axi_bready) begin
axi_bready <= 1'b1;
end else begin
axi_bready <= 1'b0;
end
end
assign mem_axi_bready = axi_bready;
always @(posedge clk) begin
if (!resetn) begin
@ -2802,7 +2816,6 @@ module picorv32_axi_adapter (
end
endmodule
/***************************************************************
* picorv32_wb
***************************************************************/