mirror of https://github.com/YosysHQ/picorv32.git
Fix bug in picorv32_pcpi_div, Add RISCV_FORMAL_ALTOPS support
This commit is contained in:
parent
ad08edd2e5
commit
7b6aa21f34
25
picorv32.v
25
picorv32.v
|
@ -2329,7 +2329,15 @@ module picorv32_pcpi_fast_mul #(
|
|||
assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1];
|
||||
assign pcpi_wait = 0;
|
||||
assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1];
|
||||
`ifdef RISCV_FORMAL_ALTOPS
|
||||
assign pcpi_rd =
|
||||
instr_mul ? (pcpi_rs1 + pcpi_rs2) ^ 32'h4d554c01 :
|
||||
instr_mulh ? (pcpi_rs1 + pcpi_rs2) ^ 32'h4d554c02 :
|
||||
instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'h4d554c03 :
|
||||
instr_mulhu ? (pcpi_rs1 + pcpi_rs2) ^ 32'h4d554c04 : 1'bx;
|
||||
`else
|
||||
assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd);
|
||||
`endif
|
||||
endmodule
|
||||
|
||||
|
||||
|
@ -2370,8 +2378,8 @@ module picorv32_pcpi_div (
|
|||
endcase
|
||||
end
|
||||
|
||||
pcpi_wait <= instr_any_div_rem;
|
||||
pcpi_wait_q <= pcpi_wait;
|
||||
pcpi_wait <= instr_any_div_rem && resetn;
|
||||
pcpi_wait_q <= pcpi_wait && resetn;
|
||||
end
|
||||
|
||||
reg [31:0] dividend;
|
||||
|
@ -2401,17 +2409,30 @@ module picorv32_pcpi_div (
|
|||
running <= 0;
|
||||
pcpi_ready <= 1;
|
||||
pcpi_wr <= 1;
|
||||
`ifdef RISCV_FORMAL_ALTOPS
|
||||
case (1)
|
||||
instr_div: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h44495601;
|
||||
instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h44495602;
|
||||
instr_rem: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h52454D01;
|
||||
instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h52454D02;
|
||||
endcase
|
||||
`else
|
||||
if (instr_div || instr_divu)
|
||||
pcpi_rd <= outsign ? -quotient : quotient;
|
||||
else
|
||||
pcpi_rd <= outsign ? -dividend : dividend;
|
||||
`endif
|
||||
end else begin
|
||||
if (divisor <= dividend) begin
|
||||
dividend <= dividend - divisor;
|
||||
quotient <= quotient | quotient_msk;
|
||||
end
|
||||
divisor <= divisor >> 1;
|
||||
`ifdef RISCV_FORMAL_ALTOPS
|
||||
quotient_msk <= quotient_msk >> 5;
|
||||
`else
|
||||
quotient_msk <= quotient_msk >> 1;
|
||||
`endif
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
Loading…
Reference in New Issue