Hardware
/
picorv32
mirror of https://github.com/YosysHQ/picorv32.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix bug in picorv32_pcpi_div, Add RISCV_FORMAL_ALTOPS support

This commit is contained in:
Clifford Wolf 2017-10-06 17:33:44 +02:00
parent ad08edd2e5
commit 7b6aa21f34
1 changed files with 23 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
picorv32.v
View File

@ -2329,7 +2329,15 @@ module picorv32_pcpi_fast_mul #(
assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1]; assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1];
assign pcpi_wait = 0; assign pcpi_wait = 0;
assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1]; assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1];
`ifdef RISCV_FORMAL_ALTOPS
assign pcpi_rd =
instr_mul ? (pcpi_rs1 + pcpi_rs2) ^ 32'h4d554c01 :
instr_mulh ? (pcpi_rs1 + pcpi_rs2) ^ 32'h4d554c02 :
instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'h4d554c03 :
instr_mulhu ? (pcpi_rs1 + pcpi_rs2) ^ 32'h4d554c04 : 1'bx;
`else
assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd); assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd);
`endif
endmodule endmodule
@ -2370,8 +2378,8 @@ module picorv32_pcpi_div (
endcase endcase
end end
pcpi_wait <= instr_any_div_rem; pcpi_wait <= instr_any_div_rem && resetn;
pcpi_wait_q <= pcpi_wait; pcpi_wait_q <= pcpi_wait && resetn;
end end
reg [31:0] dividend; reg [31:0] dividend;
@ -2401,17 +2409,30 @@ module picorv32_pcpi_div (
running <= 0; running <= 0;
pcpi_ready <= 1; pcpi_ready <= 1;
pcpi_wr <= 1; pcpi_wr <= 1;
`ifdef RISCV_FORMAL_ALTOPS
case (1)
instr_div: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h44495601;
instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h44495602;
instr_rem: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h52454D01;
instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h52454D02;
endcase
`else
if (instr_div || instr_divu) if (instr_div || instr_divu)
pcpi_rd <= outsign ? -quotient : quotient; pcpi_rd <= outsign ? -quotient : quotient;
else else
pcpi_rd <= outsign ? -dividend : dividend; pcpi_rd <= outsign ? -dividend : dividend;
`endif
end else begin end else begin
if (divisor <= dividend) begin if (divisor <= dividend) begin
dividend <= dividend - divisor; dividend <= dividend - divisor;
quotient <= quotient | quotient_msk; quotient <= quotient | quotient_msk;
end end
divisor <= divisor >> 1; divisor <= divisor >> 1;
`ifdef RISCV_FORMAL_ALTOPS
quotient_msk <= quotient_msk >> 5;
`else
quotient_msk <= quotient_msk >> 1; quotient_msk <= quotient_msk >> 1;
`endif
end end
end end
endmodule endmodule