mirror of https://github.com/YosysHQ/picorv32.git
Add correct interupt handling in RVFI trace
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picorv32.v
39
picorv32.v
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@ -1903,6 +1903,9 @@ module picorv32 #(
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end
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`ifdef RISCV_FORMAL
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reg dbg_irq_call;
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reg dbg_irq_enter;
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reg [31:0] dbg_irq_ret;
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always @(posedge clk) begin
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rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
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rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0;
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@ -1915,13 +1918,26 @@ module picorv32 #(
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rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
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rvfi_trap <= trap;
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rvfi_halt <= trap;
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rvfi_intr <= 0;
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rvfi_intr <= dbg_irq_enter;
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if (!resetn) begin
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dbg_irq_call <= 0;
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dbg_irq_enter <= 0;
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end else
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if (rvfi_valid) begin
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dbg_irq_call <= 0;
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dbg_irq_enter <= dbg_irq_call;
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end else
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if (irq_state == 1) begin
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dbg_irq_call <= 1;
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dbg_irq_ret <= next_pc;
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end
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if (!resetn) begin
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rvfi_rd_addr <= 0;
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rvfi_rd_wdata <= 0;
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end else
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if (cpuregs_write) begin
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if (cpuregs_write && !irq_state) begin
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rvfi_rd_addr <= latched_rd;
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rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0;
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end else
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@ -1930,6 +1946,22 @@ module picorv32 #(
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rvfi_rd_wdata <= 0;
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end
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casez (dbg_insn_opcode)
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32'b 0000000_?????_000??_???_?????_0001011: begin // getq
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rvfi_rs1_addr <= 0;
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rvfi_rs1_rdata <= 0;
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end
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32'b 0000001_?????_?????_???_000??_0001011: begin // setq
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rvfi_rd_addr <= 0;
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rvfi_rd_wdata <= 0;
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end
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32'b 0000010_?????_00000_???_00000_0001011: begin // retirq
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rvfi_rs1_addr <= 0;
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rvfi_rs1_rdata <= 0;
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end
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endcase
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if (!dbg_irq_call) begin
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if (dbg_mem_instr) begin
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rvfi_mem_addr <= 0;
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rvfi_mem_rmask <= 0;
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@ -1945,9 +1977,10 @@ module picorv32 #(
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rvfi_mem_wdata <= dbg_mem_wdata;
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end
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end
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end
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always @* begin
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rvfi_pc_wdata = dbg_insn_addr;
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rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr;
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end
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`endif
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