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picorv32
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Added "make test_synth"

This commit is contained in:
Clifford Wolf 2015-06-30 01:46:25 +02:00
parent 56b2b4971d
commit 997c5ce341
3 changed files with 22 additions and 2 deletions
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3
.gitignore vendored
View File

@ -17,5 +17,8 @@
/testbench.exe /testbench.exe
/testbench_sp.exe /testbench_sp.exe
/testbench_axi.exe /testbench_axi.exe
/testbench_synth.exe
/testbench.vcd /testbench.vcd
/synth.log
/synth.v
.*.swp .*.swp

14
Makefile
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@ -11,6 +11,9 @@ test_sp: testbench_sp.exe firmware/firmware.hex
test_axi: testbench_axi.exe firmware/firmware.hex test_axi: testbench_axi.exe firmware/firmware.hex
vvp -N testbench_axi.exe vvp -N testbench_axi.exe
test_synth: testbench_synth.exe firmware/firmware.hex
vvp -N testbench_synth.exe
testbench.exe: testbench.v picorv32.v testbench.exe: testbench.v picorv32.v
iverilog -o testbench.exe testbench.v picorv32.v iverilog -o testbench.exe testbench.v picorv32.v
chmod -x testbench.exe chmod -x testbench.exe
@ -23,6 +26,13 @@ testbench_axi.exe: testbench.v picorv32.v
iverilog -o testbench_axi.exe -DAXI_TEST testbench.v picorv32.v iverilog -o testbench_axi.exe -DAXI_TEST testbench.v picorv32.v
chmod -x testbench_axi.exe chmod -x testbench_axi.exe
testbench_synth.exe: testbench.v synth.v
iverilog -o testbench_synth.exe testbench.v synth.v
chmod -x testbench_synth.exe
synth.v: picorv32.v scripts/yosys/synth_sim.ys
yosys -qv3 -l synth.log scripts/yosys/synth_sim.ys
firmware/firmware.hex: firmware/firmware.bin firmware/makehex.py firmware/firmware.hex: firmware/firmware.bin firmware/makehex.py
python3 firmware/makehex.py $< > $@ python3 firmware/makehex.py $< > $@
@ -48,8 +58,8 @@ tests/%.o: tests/%.S tests/riscv_test.h tests/test_macros.h
clean: clean:
rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) \ rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) \
firmware/firmware.{elf,bin,hex,map} \ firmware/firmware.{elf,bin,hex,map} synth.v \
testbench{,_sp,_axi}.exe testbench.vcd testbench{,_sp,_axi,_synth}.exe testbench.vcd
.PHONY: test test_sp test_axi clean .PHONY: test test_sp test_axi clean

7
scripts/yosys/synth_sim.ys Normal file
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@ -0,0 +1,7 @@
# yosys synthesis script for post-synthesis simulation (make test_synth)
read_verilog picorv32.v
chparam -set ENABLE_IRQ 1 -set ENABLE_MUL 1 picorv32_axi
hierarchy -top picorv32_axi
synth
write_verilog synth.v