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Improvements in README.md
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README.md
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README.md
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@ -53,7 +53,7 @@ Parameters:
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The following Verilog module parameters can be used to configure the PicoRV32
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core.
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### ENABLE_COUNTERS (default = 1)
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#### ENABLE_COUNTERS (default = 1)
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This parameter enables support for the `RDCYCLE[H]`, `RDTIME[H]`, and
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`RDINSTRET[H]` instructions. This instructions will cause a hardware
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@ -64,43 +64,43 @@ instructions are not optional for an RV32I core. But chances are they are not
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going to be missed after the application code has been debugged and profiled.
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This instructions are optional for an RV32E core.*
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### ENABLE_REGS_16_31 (default = 1)
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#### ENABLE_REGS_16_31 (default = 1)
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This parameter enables support for registers the `x16`..`x31`. The RV32E ISA
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excludes this registers. However, the RV32E ISA spec requires a hardware trap
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for when code tries to access this registers. This is not implemented in PicoRV32.
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### ENABLE_REGS_DUALPORT (default = 1)
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#### ENABLE_REGS_DUALPORT (default = 1)
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The register file can be implemented with two or one read ports. A dual ported
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register file improves performance a bit, but can also increase the size of
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the core.
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### LATCHED_MEM_RDATA (default = 0)
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#### LATCHED_MEM_RDATA (default = 0)
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Set this to 1 if the `mem_rdata` is kept stable by the external circuit after a
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transaction. In the default configuration the PicoRV32 core only expects the
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`mem_rdata` input to be valid in the cycle with `mem_valid && mem_ready` and
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latches the value internally.
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### ENABLE_EXTERNAL_IRQ (default = 0)
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#### ENABLE_EXTERNAL_IRQ (default = 0)
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Set this to 1 to enable external IRQs.
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### ENABLE_ILLINSTR_IRQ (default = 0)
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#### ENABLE_ILLINSTR_IRQ (default = 0)
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Set this to 1 to enable the illigal instruction IRQ. This can be used for
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Set this to 1 to enable the illegal instruction IRQ. This can be used for
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software implementations of instructions such as `MUL` and `DIV`.
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### ENABLE_TIMER_IRQ (default = 0)
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#### ENABLE_TIMER_IRQ (default = 0)
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Set this to 1 to enable the built-in timer and timer IRQ.
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### PROGADDR_RESET (default = 0)
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#### PROGADDR_RESET (default = 0)
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The start address of the program.
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### PROGADDR_IRQ (default = 16)
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#### PROGADDR_IRQ (default = 16)
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The start address of the interrupt handler.
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@ -136,17 +136,16 @@ Dhrystone benchmark results: 0.309 DMIPS/MHz (544 Dhrystones/Second/MHz)
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For the Dhrystone benchmark the average CPI is 4.167.
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Custom Instructions:
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--------------------
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### IRQ Handling
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Custom Instructions for IRQ Handling
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------------------------------------
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The following custom instructions are supported when IRQs are enabled.
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The core has 4 additional 32-bit general-purpose registers `q0 .. q3`
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that are used for IRQ handling. When an IRQ triggers, the register
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`q0` contains the return address and `q1` contains the IRQ number.
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Registers `q2` and `q3` are uninitialized.
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The core has 4 additional 32-bit registers `q0 .. q3` that are used for IRQ
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handling. When an IRQ triggers, the register `q0` contains the return address
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and `q1` contains the IRQ number. Registers `q2` and `q3` are uninitialized
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and can be used as temporary storage when saving/restoring register values
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in the IRQ handler.
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#### getq rd, qs
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@ -156,7 +155,7 @@ register. The Instruction is encoded under the `custom0` opcode:
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0000000 00000 000XX 000 XXXXX 0001011
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f7 f5 qs f3 rd opcode
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Example assember code using the `custom0` mnemonic:
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Example assembler code using the `custom0` mnemonic:
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| Instruction | Assember Code |
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| ------------------| --------------------|
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@ -172,7 +171,7 @@ q-register. The Instruction is encoded under the `custom0` opcode:
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0000001 00000 XXXXX 000 000XX 0001011
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f7 f5 rs f3 qd opcode
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Example assember code using the `custom0` mnemonic:
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Example assembler code using the `custom0` mnemonic:
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| Instruction | Assember Code |
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| ------------------| --------------------|
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@ -189,7 +188,7 @@ encoded under the `custom0` opcode:
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0000010 00000 00000 000 00000 0001011
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f7 f5 rs f3 rd opcode
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Example assember code using the `custom0` mnemonic:
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Example assembler code using the `custom0` mnemonic:
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| Instruction | Assember Code |
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| ------------------| --------------------|
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@ -216,7 +215,7 @@ in the `f5` field:
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Set bits in the IRQ mask correspond to enabled interrupt sources.
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Example assember code using the `custom0` mnemonic:
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Example assembler code using the `custom0` mnemonic:
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| Instruction | Assember Code |
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| ------------------| --------------------|
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@ -236,7 +235,7 @@ Pause execution until an interrupt triggers. The Instruction is encoded under th
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0000100 00000 00000 000 00000 0001011
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f7 f5 rs f3 rd opcode
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Example assember code using the `custom0` mnemonic:
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Example assembler code using the `custom0` mnemonic:
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| Instruction | Assember Code |
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| ------------------| --------------------|
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@ -251,7 +250,7 @@ counter to zero disables the timer.
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0000101 00000 XXXXX 000 00000 0001011
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f7 f5 rs f3 rd opcode
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Example assember code using the `custom0` mnemonic:
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Example assembler code using the `custom0` mnemonic:
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| Instruction | Assember Code |
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| ------------------| --------------------|
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