mirror of https://github.com/YosysHQ/picorv32.git
Added cpu?_trap signals to tracecmp3.v
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@ -15,6 +15,7 @@ module testbench (
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always @(posedge clk)
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resetn <= 1;
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wire cpu0_trap;
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wire cpu0_mem_valid;
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wire cpu0_mem_instr;
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wire cpu0_mem_ready;
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@ -25,6 +26,7 @@ module testbench (
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wire cpu0_trace_valid;
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wire [35:0] cpu0_trace_data;
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wire cpu1_trap;
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wire cpu1_mem_valid;
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wire cpu1_mem_instr;
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wire cpu1_mem_ready;
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@ -91,6 +93,7 @@ module testbench (
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) cpu0 (
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.clk (clk ),
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.resetn (resetn ),
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.trap (cpu0_trap ),
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.mem_valid (cpu0_mem_valid ),
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.mem_instr (cpu0_mem_instr ),
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.mem_ready (cpu0_mem_ready ),
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@ -118,6 +121,7 @@ module testbench (
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) cpu1 (
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.clk (clk ),
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.resetn (resetn ),
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.trap (cpu1_trap ),
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.mem_valid (cpu1_mem_valid ),
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.mem_instr (cpu1_mem_instr ),
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.mem_ready (cpu1_mem_ready ),
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