mirror of https://github.com/YosysHQ/picorv32.git
Merge pull request #52 from olofk/testbench_wb_fixes
Testbench wb fixes
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commit
a9e0ea54cf
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@ -87,7 +87,6 @@ module picorv32_wrapper #(
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wb_ram #(
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wb_ram #(
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.depth (16384 * 4),
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.depth (16384 * 4),
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.memfile ("firmware/firmware.hex"),
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.VERBOSE (VERBOSE)
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.VERBOSE (VERBOSE)
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) ram ( // Wishbone interface
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) ram ( // Wishbone interface
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.wb_clk_i(wb_clk),
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.wb_clk_i(wb_clk),
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@ -139,6 +138,13 @@ module picorv32_wrapper #(
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.wbm_sel_o(wb_m2s_sel)
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.wbm_sel_o(wb_m2s_sel)
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);
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);
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reg [1023:0] firmware_file;
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initial begin
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if (!$value$plusargs("firmware=%s", firmware_file))
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firmware_file = "firmware/firmware.hex";
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$readmemh(firmware_file, ram.mem);
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end
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integer cycle_counter;
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integer cycle_counter;
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always @(posedge wb_clk) begin
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always @(posedge wb_clk) begin
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cycle_counter <= !wb_rst ? cycle_counter + 1 : 0;
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cycle_counter <= !wb_rst ? cycle_counter + 1 : 0;
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@ -160,6 +166,25 @@ module picorv32_wrapper #(
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end
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end
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endmodule
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endmodule
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/* ISC License
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*
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* Verilog on-chip RAM with Wishbone interface
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*
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* Copyright (C) 2014, 2016 Olof Kindgren <olof.kindgren@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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module wb_ram #(
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module wb_ram #(
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parameter depth = 256,
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parameter depth = 256,
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parameter memfile = "",
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parameter memfile = "",
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