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Faster memory model in dhrystone testbench

This commit is contained in:
Clifford Wolf 2015-06-06 19:35:07 +02:00
parent c55d537401
commit abe0465753
1 changed files with 18 additions and 18 deletions
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22
dhrystone/testbench.v
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@ -14,11 +14,11 @@ module testbench;
wire mem_valid; wire mem_valid;
wire mem_instr; wire mem_instr;
reg mem_ready; wire mem_ready;
wire [31:0] mem_addr; wire [31:0] mem_addr;
wire [31:0] mem_wdata; wire [31:0] mem_wdata;
wire [3:0] mem_wstrb; wire [3:0] mem_wstrb;
reg [31:0] mem_rdata; wire [31:0] mem_rdata;
picorv32 uut ( picorv32 uut (
.clk (clk ), .clk (clk ),
@ -36,23 +36,23 @@ module testbench;
reg [31:0] memory [0:64*1024/4-1]; reg [31:0] memory [0:64*1024/4-1];
initial $readmemh("dhry.hex", memory); initial $readmemh("dhry.hex", memory);
assign mem_ready = 1;
assign mem_rdata = memory[mem_addr >> 2];
always @(posedge clk) begin always @(posedge clk) begin
mem_ready <= 0; if (mem_valid) begin
mem_rdata <= 'bx; case (mem_addr)
if (resetn && mem_valid && !mem_ready) begin 32'h1000_0000: begin
mem_ready <= 1;
if (mem_addr == 32'h1000_0000) begin
$write("%c", mem_wdata); $write("%c", mem_wdata);
$fflush(); $fflush();
end else end
if (mem_wstrb) begin default: begin
if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0]; if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8]; if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16]; if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24]; if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
end else begin
mem_rdata <= memory[mem_addr >> 2];
end end
endcase
end end
end end