mirror of https://github.com/YosysHQ/picorv32.git
Add RVFI CSRs
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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picorv32.v
39
picorv32.v
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@ -136,6 +136,16 @@ module picorv32 #(
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output reg [ 3:0] rvfi_mem_wmask,
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output reg [31:0] rvfi_mem_rdata,
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output reg [31:0] rvfi_mem_wdata,
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output reg [63:0] rvfi_csr_mcycle_rmask,
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output reg [63:0] rvfi_csr_mcycle_wmask,
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output reg [63:0] rvfi_csr_mcycle_rdata,
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output reg [63:0] rvfi_csr_mcycle_wdata,
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output reg [63:0] rvfi_csr_minstret_rmask,
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output reg [63:0] rvfi_csr_minstret_wmask,
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output reg [63:0] rvfi_csr_minstret_rdata,
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output reg [63:0] rvfi_csr_minstret_wdata,
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`endif
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// Trace Interface
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@ -2026,6 +2036,35 @@ module picorv32 #(
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always @* begin
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rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr;
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rvfi_csr_mcycle_rmask = 0;
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rvfi_csr_mcycle_wmask = 0;
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rvfi_csr_mcycle_rdata = 0;
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rvfi_csr_mcycle_wdata = 0;
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rvfi_csr_minstret_rmask = 0;
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rvfi_csr_minstret_wmask = 0;
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rvfi_csr_minstret_rdata = 0;
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rvfi_csr_minstret_wdata = 0;
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if (rvfi_valid && rvfi_insn[6:0] == 7'b 1110011 && rvfi_insn[13:12] == 3'b010) begin
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if (rvfi_insn[31:20] == 12'h C00) begin
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rvfi_csr_mcycle_rmask = 64'h 0000_0000_FFFF_FFFF;
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rvfi_csr_mcycle_rdata = {32'h 0000_0000, rvfi_rd_wdata};
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end
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if (rvfi_insn[31:20] == 12'h C80) begin
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rvfi_csr_mcycle_rmask = 64'h FFFF_FFFF_0000_0000;
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rvfi_csr_mcycle_rdata = {rvfi_rd_wdata, 32'h 0000_0000};
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end
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if (rvfi_insn[31:20] == 12'h C02) begin
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rvfi_csr_minstret_rmask = 64'h 0000_0000_FFFF_FFFF;
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rvfi_csr_minstret_rdata = {32'h 0000_0000, rvfi_rd_wdata};
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end
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if (rvfi_insn[31:20] == 12'h C82) begin
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rvfi_csr_minstret_rmask = 64'h FFFF_FFFF_0000_0000;
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rvfi_csr_minstret_rdata = {rvfi_rd_wdata, 32'h 0000_0000};
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end
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end
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end
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`endif
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