mirror of https://github.com/YosysHQ/picorv32.git
Cleanups in dhrystone/testbench_slow_mem.v, added results to README
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@ -351,6 +351,9 @@ Dhrystone benchmark results: 0.521 DMIPS/MHz (916 Dhrystones/Second/MHz)
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For the Dhrystone benchmark the average CPI is 4.081.
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For the Dhrystone benchmark the average CPI is 4.081.
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Without using the look-ahead memory interface (usually required for max
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clock speed), this results drop to 0.305 DMIPS/MHz and 5.232 CPI.
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PicoRV32 Native Memory Interface
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PicoRV32 Native Memory Interface
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--------------------------------
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--------------------------------
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@ -13,7 +13,6 @@ module testbench;
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end
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end
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wire mem_valid;
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wire mem_valid;
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reg mem_valid_q;
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wire mem_instr;
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wire mem_instr;
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reg mem_ready;
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reg mem_ready;
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wire [31:0] mem_addr;
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wire [31:0] mem_addr;
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@ -37,12 +36,7 @@ module testbench;
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.mem_addr (mem_addr ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata ),
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.mem_rdata (mem_rdata )
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.mem_la_read (),
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.mem_la_write(),
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.mem_la_addr (),
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.mem_la_wdata(),
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.mem_la_wstrb()
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);
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);
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reg [7:0] memory [0:256*1024-1];
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reg [7:0] memory [0:256*1024-1];
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@ -56,16 +50,14 @@ module testbench;
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mem_rdata[23:16] <= 'bx;
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mem_rdata[23:16] <= 'bx;
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mem_rdata[31:24] <= 'bx;
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mem_rdata[31:24] <= 'bx;
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if (mem_valid & !mem_valid_q) begin
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if (mem_valid & !mem_ready) begin
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if (|mem_wstrb) begin
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if (|mem_wstrb) begin
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mem_ready <= 1'b1;
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mem_ready <= 1'b1;
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case (mem_addr)
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case (mem_addr)
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32'h1000_0000: begin
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32'h1000_0000: begin
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`ifndef TIMING
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$write("%c", mem_wdata);
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$write("%c", mem_wdata);
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$fflush();
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$fflush();
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`endif
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end
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end
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default: begin
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default: begin
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if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
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@ -84,12 +76,10 @@ module testbench;
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mem_rdata[31:24] <= memory[mem_addr + 3];
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mem_rdata[31:24] <= memory[mem_addr + 3];
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end
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end
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end
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end
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mem_valid_q <= mem_valid;
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end
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end
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initial begin
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initial begin
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$dumpfile("testbench.vcd");
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$dumpfile("testbench_slow_mem.vcd");
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$dumpvars(0, testbench);
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$dumpvars(0, testbench);
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end
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end
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@ -100,15 +90,4 @@ module testbench;
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$finish;
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$finish;
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end
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end
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end
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end
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`ifdef TIMING
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initial begin
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repeat (100000) @(posedge clk);
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$finish;
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end
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always @(posedge clk) begin
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if (uut.dbg_next)
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$display("## %-s %d", uut.dbg_ascii_instr ? uut.dbg_ascii_instr : "pcpi", uut.count_cycle);
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end
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`endif
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endmodule
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endmodule
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