mirror of https://github.com/YosysHQ/picorv32.git
Added ENABLE_COUNTERS64 config parameter
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@ -141,6 +141,12 @@ instructions are not optional for an RV32I core. But chances are they are not
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going to be missed after the application code has been debugged and profiled.
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This instructions are optional for an RV32E core.*
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#### ENABLE_COUNTERS64 (default = 1)
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This parameter enables support for the `RDCYCLEH`, `RDTIMEH`, and `RDINSTRETH`
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instructions. If this parameter is set to 0, and `ENABLE_COUNTERS` is set to 1,
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then only the `RDCYCLE`, `RDTIME`, and `RDINSTRET` instructions are available.
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#### ENABLE_REGS_16_31 (default = 1)
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This parameter enables support for registers the `x16`..`x31`. The RV32E ISA
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19
picorv32.v
19
picorv32.v
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@ -39,6 +39,7 @@
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module picorv32 #(
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parameter [ 0:0] ENABLE_COUNTERS = 1,
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parameter [ 0:0] ENABLE_COUNTERS64 = 1,
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parameter [ 0:0] ENABLE_REGS_16_31 = 1,
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parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
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parameter [ 0:0] LATCHED_MEM_RDATA = 0,
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@ -786,9 +787,9 @@ module picorv32 #(
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instr_rdcycle <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) ||
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(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS;
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instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) ||
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(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS;
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(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
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instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;
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instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS;
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instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
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instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
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instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
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@ -985,8 +986,10 @@ module picorv32 #(
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pcpi_timeout <= !pcpi_timeout_counter;
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end
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if (ENABLE_COUNTERS)
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if (ENABLE_COUNTERS) begin
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count_cycle <= resetn ? count_cycle + 1 : 0;
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if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;
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end
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next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
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@ -1096,8 +1099,10 @@ module picorv32 #(
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if (decoder_trigger) begin
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`debug($display("-- %-0t", $time);)
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reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
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if (ENABLE_COUNTERS)
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if (ENABLE_COUNTERS) begin
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count_instr <= count_instr + 1;
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if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0;
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end
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if (instr_jal) begin
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mem_do_rinst <= 1;
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reg_next_pc <= current_pc + decoded_imm_uj;
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@ -1157,11 +1162,11 @@ module picorv32 #(
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case (1'b1)
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instr_rdcycle:
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reg_out <= count_cycle[31:0];
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instr_rdcycleh:
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instr_rdcycleh && ENABLE_COUNTERS64:
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reg_out <= count_cycle[63:32];
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instr_rdinstr:
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reg_out <= count_instr[31:0];
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instr_rdinstrh:
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instr_rdinstrh && ENABLE_COUNTERS64:
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reg_out <= count_instr[63:32];
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endcase
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latched_store <= 1;
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@ -1711,6 +1716,7 @@ endmodule
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module picorv32_axi #(
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parameter [ 0:0] ENABLE_COUNTERS = 1,
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parameter [ 0:0] ENABLE_COUNTERS64 = 1,
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parameter [ 0:0] ENABLE_REGS_16_31 = 1,
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parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
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parameter [ 0:0] TWO_STAGE_SHIFT = 1,
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@ -1811,6 +1817,7 @@ module picorv32_axi #(
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picorv32 #(
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.ENABLE_COUNTERS (ENABLE_COUNTERS ),
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.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
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.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
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.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
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.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
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