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picorv32
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Added SBREAK handling for CATCH_ILLINSN=0

This commit is contained in:
Clifford Wolf 2016-04-13 15:09:49 +02:00
parent 262a9085bb
commit faa1c1a159
3 changed files with 13 additions and 1 deletions
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5
README.md
View File

@ -215,6 +215,11 @@ accesses.
Set this to 0 to disable the circuitry for catching illegal instructions. Set this to 0 to disable the circuitry for catching illegal instructions.
The core will still trap on an `SBREAK` instruction with this option
set to 0. With IRQs enabled, an `SBREAK` normally triggers an IRQ 1. With
this option set to 0, an `SBREAK` will trap the processor without
triggering an interrupt.
#### ENABLE_PCPI (default = 0) #### ENABLE_PCPI (default = 0)
Set this to 1 to enable the Pico Co-Processor Interface (PCPI). Set this to 1 to enable the Pico Co-Processor Interface (PCPI).

8
picorv32.v
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@ -494,7 +494,7 @@ module picorv32 #(
reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw; reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai; reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and; reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh; reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_sbreak;
reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer; reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
wire instr_trap; wire instr_trap;
@ -858,6 +858,9 @@ module picorv32 #(
instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS; instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;
instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64; instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
instr_sbreak <= !CATCH_ILLINSN && ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:7] == 'b0000000000010000000000000) ||
(COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002));
instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS; instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS; instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ; instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ;
@ -1503,6 +1506,9 @@ module picorv32 #(
end else end else
cpu_state <= cpu_state_trap; cpu_state <= cpu_state_trap;
end end
if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_sbreak) begin
cpu_state <= cpu_state_trap;
end
if (!resetn || mem_done) begin if (!resetn || mem_done) begin
mem_do_prefetch <= 0; mem_do_prefetch <= 0;

1
scripts/torture/config.py
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@ -18,6 +18,7 @@ with open("config.vh", "w") as f:
print(".TWO_CYCLE_COMPARE(%d)," % np.random.randint(2), file=f) print(".TWO_CYCLE_COMPARE(%d)," % np.random.randint(2), file=f)
print(".TWO_CYCLE_ALU(%d)," % np.random.randint(2), file=f) print(".TWO_CYCLE_ALU(%d)," % np.random.randint(2), file=f)
print(".CATCH_MISALIGN(%d)," % np.random.randint(2), file=f) print(".CATCH_MISALIGN(%d)," % np.random.randint(2), file=f)
print(".CATCH_ILLINSN(%d)," % np.random.randint(2), file=f)
print(".COMPRESSED_ISA(%d)," % compressed_isa, file=f) print(".COMPRESSED_ISA(%d)," % compressed_isa, file=f)
print(".ENABLE_MUL(%d)," % enable_mul, file=f) print(".ENABLE_MUL(%d)," % enable_mul, file=f)
print(".ENABLE_DIV(%d)" % enable_div, file=f) print(".ENABLE_DIV(%d)" % enable_div, file=f)