picorv32

Commit Graph

Author	SHA1	Message	Date
Clifford Wolf	00dd6ac38e	Added ENABLE_DIV and picorv32_pcpi_div	2016-04-10 16:54:35 +02:00
Clifford Wolf	7909b2a7d9	Merge branch 'master' into compressed	2016-04-05 11:59:42 +02:00
Clifford Wolf	714f7d9cfa	Merged axi4_memory.v and picorv32_wrapper.v back into testbench.v	2016-03-02 12:50:52 +01:00
Olof Kindgren	9591ae9f7d	Split out verilator-incompatible code to top-level testbench Verilator doesn't handle verilog code that deals with time, such as delayed signals or the repeat task. Clock and reset generation are therefore moved to a separate file that can be replaced by a verilator module. VCD generation is also affected by this.	2016-02-18 22:47:15 +01:00
Olof Kindgren	8343315aa7	Break out AXI4 memory to a separate module This commit also adds support for setting the AXI_TEST and VERBOSE defines as plusargs or parameters	2016-02-18 21:26:18 +01:00
Clifford Wolf	c4c477180e	Merged various testbench changes from compressed ISA branch	2016-02-03 16:33:01 +01:00
Clifford Wolf	8174d8fb7e	Towards compressed ISA support	2015-11-15 23:24:38 +01:00
Clifford Wolf	c48a3b2434	Removed trailing whitespaces	2015-07-02 10:49:35 +02:00
Clifford Wolf	a7f9b7fbf3	Some testbench-related improvements Patch by Larry Doolittle	2015-07-02 10:45:35 +02:00
Clifford Wolf	1f99de5117	Improvements in picorv32_pcpi_mul	2015-06-28 13:07:50 +02:00
Clifford Wolf	923ac360ff	More README stuff	2015-06-28 12:20:23 +02:00
Clifford Wolf	44571601c1	Added "make test_sp"	2015-06-26 23:54:12 +02:00
Clifford Wolf	0be990bd04	Added Pico Co-Processor Interface (PCPI)	2015-06-26 23:15:35 +02:00
Clifford Wolf	9a4a06d981	Refactoring of IRQ handling	2015-06-26 10:03:37 +02:00
Clifford Wolf	23b700cf73	Added basic IRQ support	2015-06-25 14:08:39 +02:00
Clifford Wolf	c55d537401	Improved AXI tests	2015-06-06 19:22:28 +02:00
Clifford Wolf	7fd24a96b2	Improved AXI Interface Testbench	2015-06-06 17:15:09 +02:00
Clifford Wolf	77ba5a1897	Initial import	2015-06-06 14:14:32 +02:00

18 Commits