mirror of https://github.com/YosysHQ/picorv32.git
67 lines
3.7 KiB
Markdown
67 lines
3.7 KiB
Markdown
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PicoSoC - A simple example SoC using PicoRV32
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=============================================
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This is a simple PicoRV32 example design that can run code directly from an SPI
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flash chip. This example design uses the Lattice iCE40-HX8K Breakout Board.
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The flash is mapped to the memory region starting at 0x01000000. The reset
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vector is set to 0x01100000, i.e. at the 1MB offset inside the flash memory.
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A small scratchpad memory (default 256 words, i.e. 1 kB) is mapped to address
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0x00000000.
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Run `make test` to run the test bench (and create `testbench.vcd`).
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Run `make prog` to build the configuration bit-stream and firmware images
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and upload them to a connected iCE40-HX8K Breakout Board.
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| File | Description |
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| ----------------------------- | --------------------------------------------------------------- |
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| [picosoc.v](picosoc.v) | Top-level PicoSoC Verilog module |
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| [spimemio.v](spimemio.v) | Memory controller that interfaces to external SPI flash |
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| [simpleuart.v](simpleuart.v) | Simple UART core connected directly to SoC TX/RX lines |
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| [start.s](start.s) | Assembler source for firmware.hex/firmware.bin |
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| [firmware.c](firmware.c) | C source for firmware.hex/firmware.bin |
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| [sections.lds](sections.lds) | Linker script for firmware.hex/firmware.bin |
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| [hx8kdemo.v](hx8kdemo.v) | FPGA-based example implementation on iCE40-HX8K Breakout Board |
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| [hx8kdemo.pcf](hx8kdemo.pcf) | Pin constraints for implementation on iCE40-HX8K Breakout Board |
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### Memory map:
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| Address Range | Description |
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| ------------------------ | --------------------------------------- |
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| 0x00000000 .. 0x00FFFFFF | Internal SRAM |
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| 0x01000000 .. 0x01FFFFFF | External Serial Flash |
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| 0x02000000 .. 0x02000003 | SPI Flash Controller Config Register |
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| 0x02000004 .. 0x02000007 | UART Clock Divider Register |
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| 0x02000008 .. 0x0200000B | UART Send/Recv Data Register |
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| 0x03000000 .. 0xFFFFFFFF | Memory mapped user peripherals |
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Reading from the addresses in the internal SRAM region beyond the end of the
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physical SRAM will read from the corresponding addresses in serial flash.
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Reading from the UART Send/Recv Data Register will return the last received
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byte, or -1 (all 32 bits set) when the receive buffer is empty.
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The example design (hx8kdemo.v) and generic test bench (testbench.v) have 32
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GPIO pins mapped to the 32 bit word at address 0x03000000.
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### SPI Flash Controller Config Register:
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| Bit(s) | Description |
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| -----: | --------------------------------------------------------- |
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| 31 | MEMIO Enable (reset=1, set to 0 to bit bang SPI commands) |
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| 30:23 | Reserved (read 0) |
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| 22 | DDR Enable bit (reset=0) |
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| 21 | QSPI Enable bit (reset=0) |
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| 20 | Continous Read Enable bit (reset=0) |
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| 19:16 | Number of QSPI dummy cycles (reset=0) |
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| 15:12 | Reserved (read 0) |
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| 11:8 | IO Output enable bits in bit bang mode |
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| 7:6 | Reserved (read 0) |
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| 5 | Chip select (CS) line in bit bang mode |
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| 4 | Serial clock line in bit bang mode |
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| 3:0 | IO data bits in bit bang mode |
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