mirror of https://github.com/YosysHQ/picorv32.git
64 lines
2.5 KiB
Markdown
64 lines
2.5 KiB
Markdown
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PicoRV32 - A Size-Optimized RISC-V CPU
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======================================
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PicoRV32 is a CPU core that implements the [RISC-V RV32I Instruction Set](http://riscv.org/).
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Tools (gcc, binutils, etc..) can be obtained via the [RISC-V Website](http://riscv.org/download.html#tab_tools).
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Features and Typical Applications:
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----------------------------------
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- Small (about 1000 LUTs in a 7-Series Xilinx FGPA)
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- High fMAX (>250 MHz on 7-Series Xilinx FGPAs)
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- Selectable native memory interface or AXI4-Lite master
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This CPU is meant to be used as auxiliary processor in FPGA designs and ASICs. Due
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to its high fMAX it can be integrated in most existing designs without crossing
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clock domains. When operated on a lower frequency, it will have a lot of timing
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slack and thus can be added to a design without compromising timing closure.
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For even smaller size it is possible disable support for registers `x16`..`x31` as
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well as `RDCYCLE[H]`, `RDTIME[H]`, and `RDINSTRET[H]` instructions, turning the
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processor into an RV32E core.
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*Note: In architectures that implement the register file in dedicated memory
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resources, such as many FPGAs, disabling the 16 upper registers may not further
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reduce the core size.*
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The core exists in two variations: `picorv32` and `picorv32_axi`. The former
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provides a simple native memory interface, that is easy to use in simple
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environments, and the latter provides an AXI-4 Lite Master interface that can
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easily be integrated with existing systems that are already using the AXI
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standard.
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A separate core `picorv32_axi_adapter` is provided to bridge between the native
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memory interface and AXI4. This core can be used to create custom cores that
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include one or more PicoRV32 cores together with local RAM, ROM, and
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memory-mapped peripherals, communicating with each other using the native
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interface, and communicating with the outside world via AXI4.
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Performance:
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------------
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The average Cycles per Instruction (CPI) is 6 to 8, depending on the
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application code. (Most instructions, including unconditional branches and
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not-taken conditional branches execute in 5 cycles. Memory load/store, taken
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conditional branches, JALR, and shift operations may take more than 5 cycles.)
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Dhrystone benchmark results: 0.124 DMIPS/MHz (219 Dhrystones/Second/MHz)
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*This numbers apply for setups with memory that can accomodate requests within
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one clock cycle. Slower memory will degrade the performance of the processor.*
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Todos:
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------
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- Optional IRQ support
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- Optional write-through cache
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- Optional support for compressed ISA
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