mirror of https://github.com/YosysHQ/picorv32.git
281 lines
10 KiB
Markdown
281 lines
10 KiB
Markdown
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PicoRV32 - A Size-Optimized RISC-V CPU
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======================================
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PicoRV32 is a CPU core that implements the [RISC-V RV32I Instruction Set](http://riscv.org/).
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Tools (gcc, binutils, etc..) can be obtained via the [RISC-V Website](http://riscv.org/download.html#tab_tools).
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PicoRV32 is free and open hardware licensed under the [ISC license](http://en.wikipedia.org/wiki/ISC_license)
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(a license that is similar in terms to the MIT license or the 2-clause BSD license).
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Features and Typical Applications:
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----------------------------------
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- Small (~1000 LUTs in a 7-Series Xilinx FGPA)
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- High fMAX (~250 MHz on 7-Series Xilinx FGPAs)
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- Selectable native memory interface or AXI4-Lite master
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This CPU is meant to be used as auxiliary processor in FPGA designs and ASICs. Due
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to its high fMAX it can be integrated in most existing designs without crossing
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clock domains. When operated on a lower frequency, it will have a lot of timing
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slack and thus can be added to a design without compromising timing closure.
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For even smaller size it is possible disable support for registers `x16`..`x31` as
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well as `RDCYCLE[H]`, `RDTIME[H]`, and `RDINSTRET[H]` instructions, turning the
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processor into an RV32E core.
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Furthermore it is possible to choose between a single-port and a dual-port
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register file implementation. The former provides better performance while
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the latter results in a smaller core.
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*Note: In architectures that implement the register file in dedicated memory
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resources, such as many FPGAs, disabling the 16 upper registers and/or
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disabling the dual-port register file may not further reduce the core size.*
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The core exists in two variations: `picorv32` and `picorv32_axi`. The former
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provides a simple native memory interface, that is easy to use in simple
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environments, and the latter provides an AXI-4 Lite Master interface that can
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easily be integrated with existing systems that are already using the AXI
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standard.
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A separate core `picorv32_axi_adapter` is provided to bridge between the native
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memory interface and AXI4. This core can be used to create custom cores that
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include one or more PicoRV32 cores together with local RAM, ROM, and
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memory-mapped peripherals, communicating with each other using the native
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interface, and communicating with the outside world via AXI4.
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Parameters:
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-----------
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The following Verilog module parameters can be used to configure the PicoRV32
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core.
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#### ENABLE_COUNTERS (default = 1)
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This parameter enables support for the `RDCYCLE[H]`, `RDTIME[H]`, and
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`RDINSTRET[H]` instructions. This instructions will cause a hardware
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trap (like any other unsupported instruction) if `ENABLE_COUNTERS` is set to zero.
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*Note: Strictly speaking the `RDCYCLE[H]`, `RDTIME[H]`, and `RDINSTRET[H]`
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instructions are not optional for an RV32I core. But chances are they are not
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going to be missed after the application code has been debugged and profiled.
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This instructions are optional for an RV32E core.*
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#### ENABLE_REGS_16_31 (default = 1)
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This parameter enables support for registers the `x16`..`x31`. The RV32E ISA
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excludes this registers. However, the RV32E ISA spec requires a hardware trap
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for when code tries to access this registers. This is not implemented in PicoRV32.
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#### ENABLE_REGS_DUALPORT (default = 1)
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The register file can be implemented with two or one read ports. A dual ported
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register file improves performance a bit, but can also increase the size of
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the core.
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#### LATCHED_MEM_RDATA (default = 0)
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Set this to 1 if the `mem_rdata` is kept stable by the external circuit after a
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transaction. In the default configuration the PicoRV32 core only expects the
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`mem_rdata` input to be valid in the cycle with `mem_valid && mem_ready` and
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latches the value internally.
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#### ENABLE_IRQ (default = 0)
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Set this to 1 to enable IRQs.
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#### MASKED_IRQ (default = 32'h 0000_0000)
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A 1 bit in this bitmask corresponds to a permanently disabled IRQ.
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#### PROGADDR_RESET (default = 32'h 0000_0000)
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The start address of the program.
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#### PROGADDR_IRQ (default = 32'h 0000_0010)
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The start address of the interrupt handler.
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Performance:
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------------
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*A short reminder: This core is optimized for size, not performance.*
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Unless stated otherwise, the following numbers apply to a PicoRV32 with
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ENABLE_REGS_DUALPORT active and connected to a memory that can accomodate
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requests within one clock cycle.
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The average Cycles per Instruction (CPI) is 4 to 5, depending on the mix of
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instructions in the code. The CPI numbers for the individual instructions
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can be found in the table below. The column "CPI (SP)" contains the
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CPI numbers for a core built without ENABLE_REGS_DUALPORT.
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| Instruction | CPI | CPI (SP) |
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| ---------------------| ----:| --------:|
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| direct jump (jal) | 3 | 3 |
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| ALU reg + immediate | 3 | 3 |
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| ALU reg + reg | 3 | 4 |
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| branch (not taken) | 3 | 4 |
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| memory load | 5 | 5 |
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| memory store | 5 | 6 |
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| branch (taken) | 5 | 6 |
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| indirect jump (jalr) | 6 | 6 |
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| shift operations | 4-14 | 4-15 |
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Dhrystone benchmark results: 0.309 DMIPS/MHz (544 Dhrystones/Second/MHz)
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For the Dhrystone benchmark the average CPI is 4.167.
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Custom Instructions for IRQ Handling
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------------------------------------
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*Note: The IRQ handling features in PicoRV32 do not follow the RISC-V
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Privileged ISA specification. Instead a small set of very simple custom
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instructions is used to implement IRQ handling with minimal hardware
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overhead.*
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The following custom instructions are only supported when IRQs are enabled
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via the `ENABLE_IRQ` parameter (see above).
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The PicoRV32 core has a built-in interrupt controller with 32 interrupts. An
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interrupt can be triggered by asserting the corresponding bit in the `irq`
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input of the core.
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When the interrupt handler is started, the `eoi` End Of Interrupt (EOI) signals
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for the handled interrupts go high. The `eoi` signals go low again when the
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interrupt handler returns.
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The IRQs 0-2 can be triggered internally by the following built-in interrupt sources:
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| IRQ | Interrupt Source |
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| ---:| -----------------------------------|
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| 0 | Timer Interrupt |
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| 1 | SBREAK or Illegal Instruction |
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| 2 | BUS Error (Unalign Memory Access) |
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The core has 4 additional 32-bit registers `q0 .. q3` that are used for IRQ
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handling. When an IRQ triggers, the register `q0` contains the return address
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and `q1` contains a bitmask of all active IRQs. This means one call to the interrupt
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handler might need to service more than one IRQ when more than one bit is set
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in `q1`.
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Registers `q2` and `q3` are uninitialized and can be used as temporary storage
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when saving/restoring register values in the IRQ handler.
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#### getq rd, qs
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This instruction copies the value from a q-register to a general-purpose
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register. This instruction is encoded under the `custom0` opcode:
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0000000 00000 000XX 000 XXXXX 0001011
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f7 rs2 qs f3 rd opcode
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Example assembler code using the `custom0` mnemonic:
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| Instruction | Assember Code |
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| ------------------| --------------------|
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| getq x5, q2 | custom0 5, 2, 0, 0 |
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| getq x3, q0 | custom0 3, 0, 0, 0 |
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| getq x1, q3 | custom0 1, 3, 0, 0 |
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#### setq qd, rs
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This instruction copies the value from a general-purpose register to a
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q-register. This instruction is encoded under the `custom0` opcode:
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0000001 00000 XXXXX 000 000XX 0001011
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f7 rs2 rs f3 qd opcode
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Example assembler code using the `custom0` mnemonic:
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| Instruction | Assember Code |
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| ------------------| --------------------|
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| setq q2, x5 | custom0 2, 5, 0, 1 |
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| setq q0, x3 | custom0 0, 3, 0, 1 |
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| setq q3, x1 | custom0 3, 1, 0, 1 |
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#### retirq
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Return from interrupt. This instruction copies the value from `q0`
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to the program counter and re-enables interrupts. This instruction is
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encoded under the `custom0` opcode:
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0000010 00000 00000 000 00000 0001011
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f7 rs2 rs f3 rd opcode
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Example assembler code using the `custom0` mnemonic:
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| Instruction | Assember Code |
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| ------------------| --------------------|
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| retirq | custom0 0, 0, 0, 2 |
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#### maskirq
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The "IRQ Mask" register contains a birtmask of masked (disabled) interrupts.
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This opcodes writes a new value to the irq mask register and reads the old
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value.
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Enable/disable interrupt sources. This instruction is encoded under the
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`custom0` opcode:
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0000011 00000 XXXXX 000 XXXXX 0001011
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f7 rs2 rs f3 rd opcode
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Example assembler code using the `custom0` mnemonic:
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| Instruction | Assember Code |
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| ------------------| --------------------|
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| maskirq x1, x2 | custom0 1, 2, 0, 3 |
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The processor starts with all interrupts disabled.
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An illegal instruction or bus error while the illegal instruction or bus error
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interrupt is disabled will cause the processor to halt.
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#### waitirq
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Pause execution until an interrupt triggers. This instruction is encoded under the
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`custom0` opcode. The bitmask of pending IRQs is written to `rd`.
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0000100 00000 00000 000 XXXXX 0001011
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f7 rs2 rs f3 rd opcode
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Example assembler code using the `custom0` mnemonic:
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| Instruction | Assember Code |
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| ------------------| --------------------|
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| waitirq x1 | custom0 1, 0, 0, 4 |
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#### timer
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Reset the timer counter to a new value. The counter counts down clock cycles and
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triggers the timer interrupt when transitioning from 1 to 0. Setting the
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counter to zero disables the timer. The old value of the counter is written to
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`rd`.
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0000101 00000 XXXXX 000 XXXXX 0001011
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f7 rs2 rs f3 rd opcode
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Example assembler code using the `custom0` mnemonic:
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| Instruction | Assember Code |
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| ------------------| --------------------|
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| timer x1, x2 | custom0 1, 2, 0, 5 |
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Todos:
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------
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- Optional FENCE support
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- Optional Co-Processor Interface
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- Optional write-through cache
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- Optional support for compressed ISA
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- Improved documentation and examples
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- Code cleanups and refactoring of main FSM
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