mirror of https://github.com/YosysHQ/picorv32.git
106 lines
1.8 KiB
Verilog
106 lines
1.8 KiB
Verilog
module spiflash (
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input spi_cs,
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output reg spi_miso,
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input spi_mosi,
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input spi_sclk
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);
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localparam verbose = 1;
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reg [7:0] buffer;
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integer bitcount = 0;
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integer bytecount = 0;
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reg [7:0] spi_cmd;
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reg [23:0] spi_addr;
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reg [7:0] spi_in;
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reg [7:0] spi_out;
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reg spi_io_vld;
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reg powered_up = 0;
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reg in_xfer = 0;
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// 16 MB (128Mb) Flash
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reg [7:0] memory [0:16*1024*1024-1];
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initial begin
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$readmemh("firmware.hex", memory);
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end
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task spi_action;
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begin
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if (verbose) begin
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if (bytecount == 1)
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$write("<SPI>");
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$write("<SPI:%02x", buffer);
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spi_in = buffer;
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end
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if (bytecount == 1) begin
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spi_cmd = buffer;
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if (spi_cmd == 8'hAB)
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powered_up = 1;
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if (spi_cmd == 8'hB9)
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powered_up = 0;
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end
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if (powered_up && spi_cmd == 'h03) begin
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if (bytecount == 2)
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spi_addr[23:16] = buffer;
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if (bytecount == 3)
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spi_addr[15:8] = buffer;
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if (bytecount == 4)
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spi_addr[7:0] = buffer;
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if (bytecount >= 4) begin
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buffer = memory[spi_addr];
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spi_addr = spi_addr + 1;
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end
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end
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if (verbose) begin
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$write(":%02x>", buffer);
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spi_out = buffer;
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spi_io_vld = 1;
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$fflush;
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end
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end
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endtask
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always @(spi_cs) begin
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if (spi_cs) begin
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if (verbose && in_xfer) begin
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$display("");
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$fflush;
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end
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buffer = 0;
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in_xfer = 0;
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bitcount = 0;
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bytecount = 0;
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spi_miso = 0;
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end
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end
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always @(spi_cs, spi_sclk) begin
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spi_io_vld = 0;
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if (!spi_cs && !spi_sclk) begin
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spi_miso = buffer[7];
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end
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end
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always @(posedge spi_sclk) begin
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if (!spi_cs) begin
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buffer = {buffer, spi_mosi};
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bitcount = bitcount + 1;
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if (bitcount == 8) begin
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in_xfer = 1;
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bitcount = 0;
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bytecount = bytecount + 1;
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spi_action;
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end
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end
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end
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endmodule
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