upsilon/firmware/rtl/control_loop/Makefile

# Makefile for tests and hardware verification.

.PHONY: test clean
COMMON_CPP = control_loop_math_implementation.cpp
COMMON= ${COMMON_CPP} control_loop_math_implementation.h

CONSTS_FRAC=43
E_WID=21

test: obj_dir/Vcontrol_loop_math
	obj_dir/Vcontrol_loop_math
clean:
	rm -rf obj_dir *.fst

obj_dir/Vcontrol_loop_math.mk: control_loop_math_sim.cpp ${COMMON} \
                               control_loop_math.v
	verilator --cc --exe -Wall --trace --trace-fst \
		--top-module control_loop_math \
		-GCONSTS_FRAC=${CONSTS_FRAC} -DDEBUG_CONTROL_LOOP_MATH \
		-CFLAGS -DCONSTS_FRAC=${CONSTS_FRAC} \
		-CFLAGS -DE_WID=${E_WID} \
		control_loop_math.v control_loop_math_sim.cpp ${COMMON_CPP}

obj_dir/Vcontrol_loop_math: obj_dir/Vcontrol_loop_math.mk
	cd obj_dir && make -f Vcontrol_loop_math.mk
add calculate dt module with simulation 2022-11-11 22:42:06 -05:00			`# Makefile for tests and hardware verification.`

Rewrite control_loop_math and simulate Replace specialized math nodes with single multiplier: each constant must be resized to fit in the multiplier. Simplifies design at the cost of speed. 2022-11-13 18:03:55 -05:00			`.PHONY: test clean`
add calculate dt module with simulation 2022-11-11 22:42:06 -05:00			`COMMON_CPP = control_loop_math_implementation.cpp`
			`COMMON= ${COMMON_CPP} control_loop_math_implementation.h`

Rewrite control_loop_math and simulate Replace specialized math nodes with single multiplier: each constant must be resized to fit in the multiplier. Simplifies design at the cost of speed. 2022-11-13 18:03:55 -05:00			`CONSTS_FRAC=43`
control_loop_math: fix compile errors and verify simulation 2022-11-18 19:27:29 -05:00			`E_WID=21`
add calculate dt module with simulation 2022-11-11 22:42:06 -05:00
Rewrite control_loop_math and simulate Replace specialized math nodes with single multiplier: each constant must be resized to fit in the multiplier. Simplifies design at the cost of speed. 2022-11-13 18:03:55 -05:00			`test: obj_dir/Vcontrol_loop_math`
			`obj_dir/Vcontrol_loop_math`
			`clean:`
control_loop_math: fix compile errors and verify simulation 2022-11-18 19:27:29 -05:00			`rm -rf obj_dir *.fst`
add calculate dt module with simulation 2022-11-11 22:42:06 -05:00
Rewrite control_loop_math and simulate Replace specialized math nodes with single multiplier: each constant must be resized to fit in the multiplier. Simplifies design at the cost of speed. 2022-11-13 18:03:55 -05:00			`obj_dir/Vcontrol_loop_math.mk: control_loop_math_sim.cpp ${COMMON} \`
			`control_loop_math.v`
add calculate dt module with simulation 2022-11-11 22:42:06 -05:00			`verilator --cc --exe -Wall --trace --trace-fst \`
Rewrite control_loop_math and simulate Replace specialized math nodes with single multiplier: each constant must be resized to fit in the multiplier. Simplifies design at the cost of speed. 2022-11-13 18:03:55 -05:00			`--top-module control_loop_math \`
			`-GCONSTS_FRAC=${CONSTS_FRAC} -DDEBUG_CONTROL_LOOP_MATH \`
			`-CFLAGS -DCONSTS_FRAC=${CONSTS_FRAC} \`
			`-CFLAGS -DE_WID=${E_WID} \`
			`control_loop_math.v control_loop_math_sim.cpp ${COMMON_CPP}`

			`obj_dir/Vcontrol_loop_math: obj_dir/Vcontrol_loop_math.mk`
			`cd obj_dir && make -f Vcontrol_loop_math.mk`
add calculate dt module with simulation 2022-11-11 22:42:06 -05:00