2023-06-15 12:24:35 -04:00
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# Copyright 2023 (C) Peter McGoron
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# This file is a part of Upsilon, a free and open source software project.
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# For license terms, refer to the files in `doc/copying` in the Upsilon
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# source distribution.
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2023-03-15 14:30:08 -04:00
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# Generate verilog from m4 file
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2023-05-10 14:35:57 -04:00
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#m4 -P --synclines $< | awk -v filename=$< '/^#line/ {printf("`line %d %s 0\n", $$2, filename); next} {print}' > $@
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# NOTE: f4pga yosys does not support `line directives. Use above for debug.
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2023-03-15 14:30:08 -04:00
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%.v: %.v.m4
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2023-03-15 17:08:55 -04:00
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m4 -P $< > $@
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2023-03-16 12:32:03 -04:00
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%_preprocessed.v: %.v
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verilator -P -E $< > $@
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