upsilon/firmware/rtl/common.makefile

# Generate verilog from m4 file
%.v: %.v.m4
	#m4 -P --synclines $< | awk -v filename=$< '/^#line/ {printf("`line %d %s 0\n", $$2, filename); next} {print}' > $@
	# NOTE: f4pga yosys does not support `line directives. Use above for debug.
	m4 -P $< > $@
%_preprocessed.v: %.v
	verilator -P -E $< > $@
change control_loop to m4 scripts, add common makefile 2023-03-15 14:30:08 -04:00			`# Generate verilog from m4 file`
			`%.v: %.v.m4`
pass yosys 2023-03-15 17:08:55 -04:00			#m4 -P --synclines $< \| awk -v filename=$< '/^#line/ {printf("`line %d %s 0\n", $$2, filename); next} {print}' > $@
			# NOTE: f4pga yosys does not support `line directives. Use above for debug.
			`m4 -P $< > $@`
move preprocessed generation to common makefile 2023-03-16 12:32:03 -04:00			`%_preprocessed.v: %.v`
			`verilator -P -E $< > $@`