upsilon/gateware/rtl/raster/flow.json

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{
"default_part": "XC7A35TCSG324-1",
"values": {
"top": "top"
},
"dependencies": {
"sources": [
"synth_test_top.v",
"ram_fifo_dual_port.v",
"ram_fifo.v"
],
"synth_log": "synth.log",
"pack_log": "pack.log"
},
"XC7A35TCSG324-1": {
"default_target": "bitstream",
"dependencies": {
"build_dir": "build/arty_35",
"xdc": [
"arty.xdc"
]
}
}
}