2023-01-22 23:43:51 -05:00
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# Makefile for tests and hardware verification.
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2023-04-02 17:20:26 -04:00
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include ../common.makefile
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2023-03-15 14:47:20 -04:00
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.PHONY: test clean codegen
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2023-01-22 23:43:51 -05:00
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2023-03-15 14:47:20 -04:00
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all: test codegen
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2023-03-15 02:24:28 -04:00
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test: obj_dir/Vbram_interface_sim obj_dir/Vwaveform_sim
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2023-03-15 17:08:55 -04:00
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CODEGEN_FILES=bram_interface_preprocessed.v waveform_preprocessed.v
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2023-01-22 23:43:51 -05:00
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2023-03-15 17:08:55 -04:00
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codegen: ${CODEGEN_FILES}
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2023-01-30 08:54:17 -05:00
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bram_SRC= bram_interface_sim.v dma_sim.v bram_interface.v bram_interface_sim.cpp
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2023-01-22 23:43:51 -05:00
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2023-01-30 08:54:17 -05:00
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obj_dir/Vbram_interface_sim.mk: $(bram_SRC)
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2023-01-22 23:43:51 -05:00
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verilator --cc --exe -Wall --trace --trace-fst \
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-CFLAGS -DWORD_AMNT=2048 \
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-CFLAGS -DRAM_WID=32 \
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$(bram_SRC)
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2023-01-30 08:54:17 -05:00
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obj_dir/Vbram_interface_sim: obj_dir/Vbram_interface_sim.mk
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cd obj_dir && make -f Vbram_interface_sim.mk
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./obj_dir/Vbram_interface_sim
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2023-01-22 23:43:51 -05:00
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2023-03-15 02:24:28 -04:00
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waveform_src = waveform_sim.v waveform.v bram_interface.v dma_sim.v waveform_sim.cpp ../spi/spi_slave_no_write.v
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obj_dir/Vwaveform_sim.mk: $(waveform_src)
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verilator --cc --exe -Wall --trace --trace-fst -I../spi \
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-CFLAGS -DWORD_AMNT=2048 \
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-CFLAGS -DRAM_WID=32 \
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2023-05-10 14:35:57 -04:00
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-DVERILATOR_SIMULATION \
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2023-03-15 02:24:28 -04:00
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$(waveform_src)
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obj_dir/Vwaveform_sim: obj_dir/Vwaveform_sim.mk $(waveform_src)
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cd obj_dir && make -f Vwaveform_sim.mk
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./obj_dir/Vwaveform_sim
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2023-01-22 23:43:51 -05:00
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clean:
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2023-03-15 17:08:55 -04:00
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rm -rf obj_dir/ ${CODEGEN_FILES}
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