upsilon/gateware/rtl/waveform/Makefile

37 lines
1.1 KiB
Makefile
Raw Normal View History

2023-01-22 23:43:51 -05:00
# Makefile for tests and hardware verification.
include ../common.makefile
.PHONY: test clean codegen
2023-01-22 23:43:51 -05:00
all: test codegen
2023-03-15 02:24:28 -04:00
test: obj_dir/Vbram_interface_sim obj_dir/Vwaveform_sim
2023-03-15 17:08:55 -04:00
CODEGEN_FILES=bram_interface_preprocessed.v waveform_preprocessed.v
2023-01-22 23:43:51 -05:00
2023-03-15 17:08:55 -04:00
codegen: ${CODEGEN_FILES}
bram_SRC= bram_interface_sim.v dma_sim.v bram_interface.v bram_interface_sim.cpp
2023-01-22 23:43:51 -05:00
obj_dir/Vbram_interface_sim.mk: $(bram_SRC)
2023-01-22 23:43:51 -05:00
verilator --cc --exe -Wall --trace --trace-fst \
-CFLAGS -DWORD_AMNT=2048 \
-CFLAGS -DRAM_WID=32 \
$(bram_SRC)
obj_dir/Vbram_interface_sim: obj_dir/Vbram_interface_sim.mk
cd obj_dir && make -f Vbram_interface_sim.mk
./obj_dir/Vbram_interface_sim
2023-01-22 23:43:51 -05:00
2023-03-15 02:24:28 -04:00
waveform_src = waveform_sim.v waveform.v bram_interface.v dma_sim.v waveform_sim.cpp ../spi/spi_slave_no_write.v
obj_dir/Vwaveform_sim.mk: $(waveform_src)
verilator --cc --exe -Wall --trace --trace-fst -I../spi \
-CFLAGS -DWORD_AMNT=2048 \
-CFLAGS -DRAM_WID=32 \
2023-05-10 14:35:57 -04:00
-DVERILATOR_SIMULATION \
2023-03-15 02:24:28 -04:00
$(waveform_src)
obj_dir/Vwaveform_sim: obj_dir/Vwaveform_sim.mk $(waveform_src)
cd obj_dir && make -f Vwaveform_sim.mk
./obj_dir/Vwaveform_sim
2023-01-22 23:43:51 -05:00
clean:
2023-03-15 17:08:55 -04:00
rm -rf obj_dir/ ${CODEGEN_FILES}