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upsilon/gateware/Makefile

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make lawyers happy
2023-06-15 12:24:35 -04:00
# Copyright 2023 (C) Peter McGoron
#
# This file is a part of Upsilon, a free and open source software project.
# For license terms, refer to the files in `doc/copying` in the Upsilon
# source distribution.
#
add missing .PHONY
2023-04-06 19:28:12 -04:00
.PHONY: cpu clean rtl_codegen
add devicetree generation
2022-07-12 15:22:14 -04:00
DEVICETREE_GEN_DIR=.
Makefiles depend on generated files
2022-07-13 14:11:56 -04:00
Progress on PicoRV32 1) The PicoRV32 bus was not generated correctly. Running "finalize" on the bus, which is what the SoC does, does not generate the bus logic correctly. I don't know if this is a bug or if the SoC bus generator is only meant to be used in the main SoC. Currently the bus logic is copied from the LiteX finalize code. 2) Add test micropython code to load code. 3) Removed BRAM. The Wishbone cache was messing with the direct implementation of the BRAM because the BRAM did not implement all the bus features correctly. LiteX has a Wishbone "SRAM" module, and despite it's name it can also generate BRAM if there are available BRAM. This is how the ROM and the startup RAM are implemented. The PicoRV32 ram is now using this SRAM.
2024-02-20 10:28:51 -05:00
all: build/digilent_arty/digilent_arty.bit arty.dtb mmio.py
Added makefile formatting
2023-08-23 22:09:34 -04:00
more work on linux upsilon
2023-05-30 16:01:32 -04:00
csr.json build/digilent_arty/digilent_arty.bit: soc.py
This compiles and runson the Arty A7-100
2024-02-17 21:34:37 -05:00
cd rtl && make
use add_constant() to modify network settings in SoC
2024-01-18 10:41:51 -05:00
python3 soc.py
Added makefile formatting
2023-08-23 22:09:34 -04:00
Progress on PicoRV32 1) The PicoRV32 bus was not generated correctly. Running "finalize" on the bus, which is what the SoC does, does not generate the bus logic correctly. I don't know if this is a bug or if the SoC bus generator is only meant to be used in the main SoC. Currently the bus logic is copied from the LiteX finalize code. 2) Add test micropython code to load code. 3) Removed BRAM. The Wishbone cache was messing with the direct implementation of the BRAM because the BRAM did not implement all the bus features correctly. LiteX has a Wishbone "SRAM" module, and despite it's name it can also generate BRAM if there are available BRAM. This is how the ROM and the startup RAM are implemented. The PicoRV32 ram is now using this SRAM.
2024-02-20 10:28:51 -05:00
mmio.py: csr.json csr2mp.py
unify region generation and added SPI to PicoRV32
2024-02-26 22:48:22 -05:00
python3 csr2mp.py > mmio.py
Progress on PicoRV32 1) The PicoRV32 bus was not generated correctly. Running "finalize" on the bus, which is what the SoC does, does not generate the bus logic correctly. I don't know if this is a bug or if the SoC bus generator is only meant to be used in the main SoC. Currently the bus logic is copied from the LiteX finalize code. 2) Add test micropython code to load code. 3) Removed BRAM. The Wishbone cache was messing with the direct implementation of the BRAM because the BRAM did not implement all the bus features correctly. LiteX has a Wishbone "SRAM" module, and despite it's name it can also generate BRAM if there are available BRAM. This is how the ROM and the startup RAM are implemented. The PicoRV32 ram is now using this SRAM.
2024-02-20 10:28:51 -05:00
add makefile; condense LiteX CSRs
2022-07-12 13:29:26 -04:00
clean:
add ssh key
2023-06-22 15:59:06 -04:00
rm -rf build csr.json arty.dts arty.dtb mmio.py
more work on linux upsilon
2023-05-30 16:01:32 -04:00
arty.dts: csr.json
firmware/Makefile: update
2023-05-30 16:50:30 -04:00
litex_json2dts_linux csr.json > arty.dts
Added makefile formatting
2023-08-23 22:09:34 -04:00
more work on linux upsilon
2023-05-30 16:01:32 -04:00
arty.dtb: arty.dts
dtc -O dtb -o arty.dtb arty.dts