upsilon/gateware/Makefile

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Makefile
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.PHONY: cpu clean rtl_codegen
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DEVICETREE_GEN_DIR=.
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all: rtl_codegen build/digilent_arty/digilent_arty.bit arty.dtb pin_io.c
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rtl_codegen:
cd rtl && make
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csr.json build/digilent_arty/digilent_arty.bit: soc.py
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TFTP_SERVER_PORT=6969 python3 soc.py
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clean:
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rm -rf build csr.json overlay.config overlay.dts pin_io.h arty.dts arty.dtb
cd rtl && make clean
test:
cd rtl && make test
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arty.dts: csr.json
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litex_json2dts_linux csr.json > arty.dts
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arty.dtb: arty.dts
dtc -O dtb -o arty.dtb arty.dts
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pin_io.c: csr.json generate_csr_locations.py
python3 generate_csr_locations.py > pin_io.c