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disable test clock by default

This commit is contained in:
Peter McGoron 2023-05-11 15:31:52 -04:00
parent a58e32fdfe
commit 0a9125355f
1 changed files with 5 additions and 23 deletions
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28
firmware/rtl/base/base.v.m4
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@ -296,30 +296,9 @@ m4_dac_switch(DAC_PORTS, 6);
m4_dac_switch(DAC_PORTS, 7); m4_dac_switch(DAC_PORTS, 7);
initial test_clock <= 0; initial test_clock <= 0;
reg [8-1:0] counter = 0;
/* `ifdef MAKE_TEST_CLOCK
always @ (posedge clk) begin reg [8-1:0] counter = 0;
if (!rst_L) begin
counter <= 0;
test_clock <= 0;
end else if (counter >= ADC_CYCLE_HALF_WAIT) begin
counter <= 0;
test_clock <= !test_clock;
end else begin
counter <= counter + 1;
end
end
*/
/*
always @ (posedge clk) begin
if(!rst_L) begin
test_clock <= 0;
end else begin
test_clock <= !test_clock;
end
end
*/
always @ (posedge clk) begin always @ (posedge clk) begin
if (!rst_L) begin if (!rst_L) begin
counter <= 0; counter <= 0;
@ -333,6 +312,9 @@ always @ (posedge clk) begin
end end
end end
end end
`else
assign test_clock = 0;
`endif
m4_adc_switch(ADC_TYPE1_WID, 0, ADC_PORTS_CONTROL_LOOP); m4_adc_switch(ADC_TYPE1_WID, 0, ADC_PORTS_CONTROL_LOOP);
m4_adc_switch(ADC_TYPE1_WID, 1, ADC_PORTS); m4_adc_switch(ADC_TYPE1_WID, 1, ADC_PORTS);