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codegen

This commit is contained in:
Peter McGoron 2023-03-15 14:57:08 -04:00
parent ca8078f9d6
commit fbbd41c95e
5 changed files with 18 additions and 6 deletions
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8
firmware/Makefile
View File

@ -2,11 +2,11 @@
DEVICETREE_GEN_DIR=. DEVICETREE_GEN_DIR=.
all: rtl/base/base.v build/digilent_arty/digilent_arty.bit overlay.dts overlay.config pin_io.h all: rtl_codegen build/digilent_arty/digilent_arty.bit overlay.dts overlay.config pin_io.h
rtl/base/base.v: rtl_codegen:
cd rtl/base && make cd rtl && make
build/digilent_arty/digilent_arty.bit: rtl/base/base.v soc.py build/digilent_arty/digilent_arty.bit: rtl_codegen soc.py
python3 soc.py python3 soc.py
clean: clean:
rm -rf build csr.json overlay.config overlay.dts pin_io.h rm -rf build csr.json overlay.config overlay.dts pin_io.h

10
firmware/rtl/Makefile Normal file
View File

@ -0,0 +1,10 @@
all: make_base make_control_loop make_waveform
make_base:
cd base && make codegen
make_spi:
cd spi && make codegen
make_control_loop:
cd control_loop && make codegen
make_waveform:
cd waveform && make codegen

2
firmware/rtl/base/Makefile
View File

@ -1,5 +1,7 @@
.PHONY: lint .PHONY: lint
include ../common.makefile include ../common.makefile
codegen: base.v
base.v: base.v.m4 base.v: base.v.m4
lint: base.v lint: base.v
verilator --lint-only base.v -I../spi -I../control_loop -I../waveform verilator --lint-only base.v -I../spi -I../control_loop -I../waveform

2
firmware/rtl/spi/Makefile
View File

@ -6,7 +6,7 @@ all: test codegen
test: obj_dir/Vspi_switch test: obj_dir/Vspi_switch
codegen: spi_master_ss_preprocessed.v spi_master_preprocessed.v \ codegen: spi_master_ss_preprocessed.v spi_master_preprocessed.v \
spi_master_ss_no_write_preprocessed.v spi_master_ss_no_write_preprocessed.v spi_switch_preprocessed.v
%_preprocessed.v: %.v %_preprocessed.v: %.v
verilator -E $< > $@ verilator -E $< > $@

2
firmware/soc.py
View File

@ -332,7 +332,7 @@ class CryoSNOM1SoC(SoCCore):
csr_address_width=14, csr_address_width=14,
csr_paging=0x800, csr_paging=0x800,
csr_ordering="big", csr_ordering="big",
timer_uptime = True)e timer_uptime = True)
# This initializes the connection to the physical DRAM interface. # This initializes the connection to the physical DRAM interface.
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3", memtype = "DDR3",