 Peter McGoron
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96e9a3d043
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raster simulate
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2022-12-23 20:22:48 +00:00 |
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Peter McGoron
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013774e28b
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raster_sim: rewrite to fit new module definitions
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2022-12-21 05:56:49 +00:00 |
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Peter McGoron
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a79ace9568
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raster_cmds: add
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2022-12-21 05:24:33 +00:00 |
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Peter McGoron
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a918d74f05
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introduce control interface; pack adc_data bits into large vector instead of an array
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2022-12-21 05:16:15 +00:00 |
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Peter McGoron
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ac0ed9e2a7
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yosys does not support input arrays
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2022-12-20 06:25:45 +00:00 |
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Peter McGoron
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a2acccbca6
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misc
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2022-12-20 06:07:54 +00:00 |
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Peter McGoron
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4ba004336c
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ram_shim: simulate
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2022-12-20 05:51:05 +00:00 |
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Peter McGoron
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15480f11da
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ram_fifo: add empty and full ports
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2022-12-18 06:06:44 +00:00 |
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Peter McGoron
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1be89f314c
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simulate and verify ram_fifo and ram_fifo_dual_port
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2022-12-17 18:39:58 +00:00 |
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Peter McGoron
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60404cd026
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ram_fifo.v: add simulator debugging checks
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2022-12-17 10:18:15 -05:00 |
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Peter McGoron
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f0f1750a9a
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add ram_fifo_dual_port wrapper to single port FIFO
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2022-12-17 10:03:06 -05:00 |
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Peter McGoron
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3612148ee1
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raster/ram_fifo: correct misspelling
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2022-12-17 09:56:57 -05:00 |
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Peter McGoron
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644f4142a2
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raster work
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2022-12-17 00:46:04 +00:00 |
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Peter McGoron
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ffdf4fb2f2
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import Xilinx FIFO36E1 simulation
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2022-12-16 20:46:00 +00:00 |
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Peter McGoron
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59b6efce7e
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raster_sim.v: add and lint
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2022-11-26 12:00:10 -05:00 |
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Peter McGoron
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a12fbf8af2
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ram_shim: add and lint
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2022-11-26 11:53:57 -05:00 |
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Peter McGoron
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c8d7572db5
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raster.v: lint
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2022-11-26 11:47:06 -05:00 |
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Peter McGoron
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9282c33cce
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add ram shim
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2022-11-24 11:07:30 -05:00 |
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Peter McGoron
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6ad2de97cf
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sketch out raster scan
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2022-11-24 00:50:21 -05:00 |
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Peter McGoron
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029cc53c5f
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some more changes
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2022-10-17 00:44:30 -04:00 |