Commit Graph

13 Commits

Author SHA1 Message Date
Peter McGoron 0cfa172a89 This compiles and runson the Arty A7-100 2024-02-18 02:34:37 +00:00
Peter McGoron 4e3df09bb8 more cleanup and bug finding 2024-02-08 12:57:22 +00:00
Peter McGoron c3980f64da Correctly finalize picorv32 module
I think LiteX's SoCIORegions are reserved regions. Non-cached regions
are then placed inside these reserved regions. Each module also has
a "do_finalize" method that runs at code generation.
2024-02-04 14:47:39 +00:00
Peter McGoron 9f76e03028 Minor SPI fixes and Interconnect fix
The previous code did not properly assign all values on all cases,
and did not properly assign values (master interfaces, which are
poorly named because they are the interfaces to the master, connect
to the slave lines directly in the interconnect)
2024-02-03 00:33:52 +00:00
Peter McGoron 0bb27e9b03 use add_constant() to modify network settings in SoC 2024-01-18 10:41:51 -05:00
Adam Mooers a9c6c1080c Added makefile formatting 2023-08-23 22:09:34 -04:00
Adam Mooers e6d88df57a csr_bitdwidth.json appears to have been superceded by mmio_descr.py 2023-08-08 17:05:47 -04:00
Peter McGoron 8b8e14bc7f z output reading 2023-06-27 17:50:55 -04:00
Peter McGoron addd660bf2 todo.md 2023-06-22 17:18:38 -04:00
Peter McGoron 9c294be58d add ssh key 2023-06-22 15:59:06 -04:00
Peter McGoron 5717ef59df csr to micropython 2023-06-21 18:47:52 -04:00
Peter McGoron 2cdbc1ae9f make lawyers happy 2023-06-15 12:24:35 -04:00
Peter McGoron a560e51991 firmware is a form of software; gateware is the equivalent for FGPAs 2023-06-14 15:31:49 -04:00