Peter McGoron
15b8fcbe7e
reset pins and test clock
2023-05-10 14:35:57 -04:00
Peter McGoron
953e42b80c
change control_loop to m4 scripts, add common makefile
2023-03-15 18:30:08 +00:00
Peter McGoron
5909f548d5
control loop simulator passes lint
2022-11-21 21:41:50 -05:00
Peter McGoron
0c10dc921c
more work on control_loop
...
* Make SPI masters internal to control loop module
* Rename commands to use I isntead of alpha
* add ADC value -> DAC value conversion to control loop math
2022-11-18 19:11:56 -05:00
Peter McGoron
45f815c5d3
changes
2022-11-11 21:57:58 -05:00
Peter McGoron
0a435f6dc8
rename control loop verilog simulation top level module to more descriptive name
2022-10-22 01:58:37 -04:00
Peter McGoron