Peter McGoron
9f76e03028
Minor SPI fixes and Interconnect fix
...
The previous code did not properly assign all values on all cases,
and did not properly assign values (master interfaces, which are
poorly named because they are the interfaces to the master, connect
to the slave lines directly in the interconnect)
2024-02-03 00:33:52 +00:00
Peter McGoron
fbd3dcef2e
picorv32 integration, take 1
2024-02-02 15:24:18 -05:00
Peter McGoron
9db87cb8ee
bram: integrate into SoC using Wishbone bus, and note alignment
2024-01-21 04:38:34 +00:00
Peter McGoron
63a347a18f
fix Makefile bram codegen
2024-01-20 20:43:12 +00:00
Peter McGoron
03d9d7ea8f
add bram
2024-01-20 15:23:40 -05:00
de2f3afd1f
Removed reference to non-existent file
2023-08-07 23:49:18 -04:00
Peter McGoron
cf95a0fd20
refactor compiles
2023-06-28 18:49:26 -04:00
Peter McGoron
054609a459
refactor control loop interface
2023-06-28 17:38:41 -04:00
Peter McGoron
8b8e14bc7f
z output reading
2023-06-27 17:50:55 -04:00
Peter McGoron
1a97dfa5aa
patch control loop math to newdac widths
2023-06-27 16:01:04 -04:00
Peter McGoron
2b698fc08a
rewrite pins
2023-06-23 14:51:35 -04:00
Peter McGoron
d76c1f8ad1
documentation
2023-06-21 17:04:54 -04:00
Peter McGoron
93d9349430
rename hardware dockerfile pt 2
2023-06-20 13:14:26 -04:00
Peter McGoron
13286b940f
fix misc errors
2023-06-20 13:10:12 -04:00
Peter McGoron
2cdbc1ae9f
make lawyers happy
2023-06-15 12:24:35 -04:00
Peter McGoron
65e160474b
remove test clock and fix make clean failing
2023-06-15 11:22:59 -04:00
Peter McGoron
0a53be49a6
control_loop/intro.md: change directory name
2023-06-14 15:36:16 -04:00
Peter McGoron
a560e51991
firmware is a form of software; gateware is the equivalent for FGPAs
2023-06-14 15:31:49 -04:00
Peter McGoron
Adam Mooers