Commit Graph

60 Commits

Author SHA1 Message Date
Peter McGoron 2e98c0229d Upsilon standard library; integrate waveform; overhaul code generation
1. Add a new Upsilon MicroPython standard library in the linux/
   subdirectory. This puts all the submodules into classes with methods
   for ease of access.
2. Totally rewrite mmio.py code generation. Instead of just dumping
   registers, the build system now instantiates classes which
   encapsulate the module in question.
3. Split the PicoRV32 special register interface away from the PicoRV32.
   It is now the PeekPokeInterface, which will be used in the future to
   implement register control for Waveform and SPI.
4. Integrate Waveform into the design. Has not been tested yet.
2024-03-11 04:31:30 +00:00
Peter McGoron 487d638aa5 Integrate Waveform into SoC; Rework PreemptiveInterface
New master buses can be added to PreemptiveInterface throughout the
code, simplifying the main SoC code. This removes the requirement that
the amount of masters to the interface needs to be known at
instantiation time.
2024-03-06 21:17:51 +00:00
Peter McGoron 75d7f298e2 Documentation and register location generation 2024-02-28 13:28:06 +00:00
Peter McGoron da1e9238ab unify region generation and added SPI to PicoRV32 2024-02-27 03:48:22 +00:00
Peter McGoron 6f61d7db7a Documentation, fix parameter passing
1. Started writing a lot of documentation on how Upsilon is
   structured. This will replace the very outdated documentation.
2. Fixed parameter access and writing. This is also a more generic
   interface that can be used for Pico CPUs that implement different
   routines.
2024-02-26 06:02:48 +00:00
Peter McGoron 6b9e594b50 Successfully read PicoRV32 registers 2024-02-26 00:47:43 +00:00
Peter McGoron 88e3d15dd8 Get PicoRV32 to execute code
1. Update LiteX to 2023.12. This update adds wishbone bus addressing
   modes. Before this update, all wishbone buses used word addressing.
   For example, 0x0 mapped to word 0, 0x0 mapped to word 1, etc. This
   caused problems with the PicoRV32 and other modules, which are byte
   addressed.
2. Use adapter to convert between byte and word addressing. The SRAM is
   word addressed. The PicoRV32 shifts the address down by two bits to
   address the correct word. The PicoRV32 core seems to expect this.
3. Add debug register output. This is not working yet.
4. Use LiteX PicoRV32 wishbone adapter instead of PicoRV32 default. This
   seems to be simpler (combinatorial not synchronous).
5. Add some documentation.
6. Seperate config to new config file.
2024-02-25 18:58:34 +00:00
Peter McGoron 3785e3498d reorganize litex code 2024-02-22 15:35:31 +00:00
Peter McGoron 06cf8807c3 Progress on PicoRV32
1) The PicoRV32 bus was not generated correctly. Running "finalize" on
   the bus, which is what the SoC does, does not generate the bus logic
   correctly. I don't know if  this is a bug or if the SoC bus generator is
   only meant to be used in the main SoC.

   Currently the bus logic is copied from the LiteX finalize code.

2) Add test micropython code to load code.

3) Removed BRAM. The Wishbone cache was messing with the direct
   implementation of the BRAM because the BRAM did not implement all the
   bus features correctly. LiteX has a Wishbone "SRAM" module, and despite
   it's name it can also generate BRAM if there are available BRAM. This is
   how the ROM and the startup RAM are implemented. The PicoRV32 ram
   is now using this SRAM.
2024-02-20 15:36:53 +00:00
Peter McGoron 0bb27e9b03 use add_constant() to modify network settings in SoC 2024-01-18 10:41:51 -05:00
Adam Mooers e4a92f5e16 Fixed ip address in host config 2023-08-16 16:27:05 -04:00
Adam Mooers e0c3bedcee Updated makefile to automatically select the right openFPGALoader 2023-08-16 15:49:44 -04:00
Adam Mooers 7ef5803cd3 Migrated changes from the upsilon-docker repo to this repo 2023-08-15 17:32:25 -04:00
Adam Mooers 3d00a65147 Revert "Removed docker readme because it is maintained in upsilon-docker repo"
This reverts commit 9f2ad01907.
2023-08-08 23:56:01 -04:00
Adam Mooers 9f2ad01907 Removed docker readme because it is maintained in upsilon-docker repo 2023-08-08 23:44:41 -04:00
Peter McGoron 054609a459 refactor control loop interface 2023-06-28 17:38:41 -04:00
Peter McGoron 1a97dfa5aa patch control loop math to newdac widths 2023-06-27 16:01:04 -04:00
Peter McGoron 291329b49e move organization.md to README.md 2023-06-27 13:24:26 -04:00
Peter McGoron 130e1775ac refactor csr2mp and docker Makefile 2023-06-26 15:49:20 -04:00
Peter McGoron f30f6f1ad5 zero scan and documentation 2023-06-23 18:15:53 -04:00
Peter McGoron 2b698fc08a rewrite pins 2023-06-23 14:51:35 -04:00
Peter McGoron addd660bf2 todo.md 2023-06-22 17:18:38 -04:00
Peter McGoron 9c294be58d add ssh key 2023-06-22 15:59:06 -04:00
Peter McGoron d76c1f8ad1 documentation 2023-06-21 17:04:54 -04:00
Peter McGoron 205c71b0fd fixedpoint.py: license 2023-06-20 13:24:22 -04:00
Peter McGoron dc1e8bae8c docker documentation 2023-06-20 13:23:43 -04:00
Peter McGoron 9c9b28116e documentation 2023-06-15 13:08:01 -04:00
Peter McGoron 2cdbc1ae9f make lawyers happy 2023-06-15 12:24:35 -04:00
Peter McGoron cd3f6d8cf9 move GUIDELINES.md to doc/verilog_manual.md 2023-06-15 11:46:48 -04:00
Peter McGoron d4310f429c add organization.md 2023-06-15 11:13:46 -04:00
Peter McGoron 388e495296 update docker documentation 2023-06-15 11:13:27 -04:00
Peter McGoron a560e51991 firmware is a form of software; gateware is the equivalent for FGPAs 2023-06-14 15:31:49 -04:00
Peter McGoron 59a7ca9de5 remove setup_client.sh 2023-06-14 15:27:34 -04:00
Peter McGoron a96736fdfb move copying to doc/copying 2023-06-14 15:27:20 -04:00
Peter McGoron 6db818b629 import upsilon_docker repository 2023-06-14 15:13:16 -04:00
Peter McGoron e273324bf6 this has to be almost entirely rewritten 2023-06-12 13:09:45 -04:00
Peter McGoron 0f761744a9 sucessfully boot MAINLINE Linux! 2023-06-05 16:50:08 -04:00
Peter McGoron a1ff0b77c3 licensing 2023-05-29 13:56:11 -04:00
Peter McGoron 5178594215 proper CSR location generation 2023-05-16 15:02:05 -04:00
Peter McGoron d23ed43574 maintenance manual 2023-05-16 14:47:32 -04:00
Peter McGoron 0d0459584b properly name boot binary 2023-05-11 14:37:46 -04:00
Peter McGoron e1d09495da update boothmul properly; add clean to make; hardware notes 2023-05-11 14:37:32 -04:00
Peter McGoron f6a4a6bbea add setup_client.sh 2023-05-11 12:08:12 -04:00
Peter McGoron f0624bf664 adc debugging 2023-05-11 11:43:30 -04:00
Peter McGoron 51d31b9129 manual 2023-04-20 15:20:28 -04:00
Peter McGoron ab4c23fa14 fix compile errors 2023-04-18 15:47:57 -04:00
Peter McGoron ce057c4066 manual: add CSR info 2023-04-08 17:31:29 +00:00
Peter McGoron dd15bef2e9 manual: reorganize 2023-04-08 15:42:04 +00:00
Peter McGoron 2dcb3fa4bf manual: add logging 2023-04-08 15:38:06 +00:00
Peter McGoron 576aca9ac6 fix thread spawning bug 2023-04-07 15:21:56 -04:00