 Peter McGoron
|
e6c57ffa63
|
soc.py: cleanup CSR generation
|
2023-04-08 17:31:12 +00:00 |
|
Peter McGoron
|
04b439a857
|
soc.py: documentation
|
2023-04-08 16:38:24 +00:00 |
|
Peter McGoron
|
79b71c7b0c
|
manual
|
2023-04-06 19:14:01 -04:00 |
|
Peter McGoron
|
0f86a60510
|
compile verilog
|
2023-04-03 15:29:20 -04:00 |
|
Peter McGoron
|
11f7cfd388
|
refactor soc.py base.v interface
|
2023-04-02 21:35:51 +00:00 |
|
Peter McGoron
|
55fc252382
|
pass yosys
|
2023-03-15 17:08:55 -04:00 |
|
Peter McGoron
|
fbbd41c95e
|
codegen
|
2023-03-15 14:57:22 -04:00 |
|
Peter McGoron
|
ca8078f9d6
|
quick hack: pre-prepreprocess verilog files
|
2023-03-15 18:47:20 +00:00 |
|
Peter McGoron
|
7af907ffb4
|
soc.py: fix syntax errors
|
2023-03-15 03:04:27 -04:00 |
|
Peter McGoron
|
fefa6409cf
|
soc.py: add missing waveform pins
|
2023-03-15 06:30:59 +00:00 |
|
Peter McGoron
|
90a49b6091
|
test and simulate spi_switch
|
2023-03-14 15:42:41 +00:00 |
|
Peter McGoron
|
295eb8fad8
|
add base.v
|
2023-03-09 04:17:41 +00:00 |
|
Peter McGoron
|
7ca119d45f
|
soc.py legal
|
2022-09-17 00:58:15 -04:00 |
|
Peter McGoron
|
01cbcb5fae
|
add verilog SPI
|
2022-07-21 17:07:52 -04:00 |
|
Peter McGoron
|
592939f5bd
|
change pinout
|
2022-07-14 15:10:58 -04:00 |
|
Peter McGoron
|
930b5ec8af
|
cleanup
|
2022-07-12 13:30:28 -04:00 |