 Peter McGoron
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5178594215
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proper CSR location generation
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2023-05-16 15:02:05 -04:00 |
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Peter McGoron
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d0ec4cca9e
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convert differential outputs to single ended outputs
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2023-05-11 16:47:24 -04:00 |
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Peter McGoron
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e1d09495da
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update boothmul properly; add clean to make; hardware notes
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2023-05-11 14:37:32 -04:00 |
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Peter McGoron
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f0624bf664
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adc debugging
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2023-05-11 11:43:30 -04:00 |
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Peter McGoron
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15b8fcbe7e
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reset pins and test clock
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2023-05-10 14:35:57 -04:00 |
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Peter McGoron
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40fd1ab6fe
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add debug clock
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2023-04-20 15:20:42 -04:00 |
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Peter McGoron
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ab4c23fa14
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fix compile errors
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2023-04-18 15:47:57 -04:00 |
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Peter McGoron
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be4ed8afcf
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soc.py: fix compile errors
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2023-04-13 12:20:19 -04:00 |
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Peter McGoron
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e6c57ffa63
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soc.py: cleanup CSR generation
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2023-04-08 17:31:12 +00:00 |
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Peter McGoron
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04b439a857
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soc.py: documentation
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2023-04-08 16:38:24 +00:00 |
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Peter McGoron
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79b71c7b0c
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manual
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2023-04-06 19:14:01 -04:00 |
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Peter McGoron
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0f86a60510
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compile verilog
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2023-04-03 15:29:20 -04:00 |
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Peter McGoron
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11f7cfd388
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refactor soc.py base.v interface
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2023-04-02 21:35:51 +00:00 |
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Peter McGoron
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55fc252382
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pass yosys
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2023-03-15 17:08:55 -04:00 |
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Peter McGoron
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fbbd41c95e
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codegen
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2023-03-15 14:57:22 -04:00 |
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Peter McGoron
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ca8078f9d6
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quick hack: pre-prepreprocess verilog files
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2023-03-15 18:47:20 +00:00 |
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Peter McGoron
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7af907ffb4
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soc.py: fix syntax errors
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2023-03-15 03:04:27 -04:00 |
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Peter McGoron
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fefa6409cf
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soc.py: add missing waveform pins
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2023-03-15 06:30:59 +00:00 |
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Peter McGoron
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90a49b6091
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test and simulate spi_switch
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2023-03-14 15:42:41 +00:00 |
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Peter McGoron
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295eb8fad8
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add base.v
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2023-03-09 04:17:41 +00:00 |
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Peter McGoron
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7ca119d45f
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soc.py legal
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2022-09-17 00:58:15 -04:00 |
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Peter McGoron
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01cbcb5fae
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add verilog SPI
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2022-07-21 17:07:52 -04:00 |
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Peter McGoron
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592939f5bd
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change pinout
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2022-07-14 15:10:58 -04:00 |
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Peter McGoron
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930b5ec8af
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cleanup
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2022-07-12 13:30:28 -04:00 |