Commit Graph

296 Commits

Author SHA1 Message Date
Peter McGoron f5b14d51ab picorv32 now runs: debugging outputs 2024-02-22 04:58:59 +00:00
Peter McGoron 67c670cb5c Use Decoder and custom region code for PicoRV32
The PicoRV32 SoC bus generator conflicts with the main SoC bus
generator, which causes the address locations in the generated verilog file
to be different from the set locations. This code uses custom region
classes in soc.py and the Decoder class directly, which is similar to
what the finalization of the SoC class uses, and is based on the LiteEth
code does.
2024-02-21 23:39:21 +00:00
Peter McGoron 06cf8807c3 Progress on PicoRV32
1) The PicoRV32 bus was not generated correctly. Running "finalize" on
   the bus, which is what the SoC does, does not generate the bus logic
   correctly. I don't know if  this is a bug or if the SoC bus generator is
   only meant to be used in the main SoC.

   Currently the bus logic is copied from the LiteX finalize code.

2) Add test micropython code to load code.

3) Removed BRAM. The Wishbone cache was messing with the direct
   implementation of the BRAM because the BRAM did not implement all the
   bus features correctly. LiteX has a Wishbone "SRAM" module, and despite
   it's name it can also generate BRAM if there are available BRAM. This is
   how the ROM and the startup RAM are implemented. The PicoRV32 ram
   is now using this SRAM.
2024-02-20 15:36:53 +00:00
Peter McGoron 0cfa172a89 This compiles and runson the Arty A7-100 2024-02-18 02:34:37 +00:00
Peter McGoron 4e3df09bb8 more cleanup and bug finding 2024-02-08 12:57:22 +00:00
Peter McGoron a10ad772bc boot currently loops at LiteX logo: this fixes it 2024-02-04 18:59:35 +00:00
Peter McGoron 7af775e46d update.gitignore 2024-02-04 17:10:08 +00:00
Peter McGoron d06e0a8589 update README.md 2024-02-04 17:00:35 +00:00
Peter McGoron 2f92199c37 write picorv32 test code 2024-02-04 16:54:10 +00:00
Peter McGoron f7d6fbee2f remove explicit finalize, is not needed and probably out of order 2024-02-04 14:50:19 +00:00
Peter McGoron c3980f64da Correctly finalize picorv32 module
I think LiteX's SoCIORegions are reserved regions. Non-cached regions
are then placed inside these reserved regions. Each module also has
a "do_finalize" method that runs at code generation.
2024-02-04 14:47:39 +00:00
Peter McGoron 9f76e03028 Minor SPI fixes and Interconnect fix
The previous code did not properly assign all values on all cases,
and did not properly assign values (master interfaces, which are
poorly named because they are the interfaces to the master, connect
to the slave lines directly in the interconnect)
2024-02-03 00:33:52 +00:00
Peter McGoron 68ce1f4f64 Change SoC IO Region declarations
LiteX has some distinction between SoCIORegions and SoCRegions that
I don't quite get. SoCRegion has to be cached, SoCIORegion is not
cached. LiteX (Migen?) also does not allow you to reach into
submodules to read values.
2024-02-02 23:38:42 +00:00
Peter McGoron b4a8fdab56 fix misc build errors 2024-02-02 22:46:58 +00:00
Peter McGoron fbd3dcef2e picorv32 integration, take 1 2024-02-02 15:24:18 -05:00
Peter McGoron 9db87cb8ee bram: integrate into SoC using Wishbone bus, and note alignment 2024-01-21 04:38:34 +00:00
Peter McGoron 63a347a18f fix Makefile bram codegen 2024-01-20 20:43:12 +00:00
Peter McGoron 8c7f57c8e9 fix compile errors for soc.py 2024-01-20 20:35:16 +00:00
Peter McGoron 565847f7c5 merge ip changes 2024-01-20 20:28:43 +00:00
Peter McGoron 03d9d7ea8f add bram 2024-01-20 15:23:40 -05:00
Peter McGoron cd2be977bc fix SoC compile 2024-01-18 19:48:34 +00:00
Peter McGoron 0bb27e9b03 use add_constant() to modify network settings in SoC 2024-01-18 10:41:51 -05:00
Adam Mooers 8b5204978b
Merge pull request #2 from AdamMooers/initial_functionality
Initial functionality
2023-08-23 22:11:44 -04:00
Adam Mooers a9c6c1080c Added makefile formatting 2023-08-23 22:09:34 -04:00
Adam Mooers 2863c9a2d2 Fixed bug where scp silently switches to sftp on new version of openssh 2023-08-20 00:47:04 -04:00
Adam Mooers b1fb245908 Cleaned up Makefile formatting and clarified tar comment 2023-08-17 11:53:18 -04:00
Adam Mooers e4a92f5e16 Fixed ip address in host config 2023-08-16 16:27:05 -04:00
Adam Mooers e0c3bedcee Updated makefile to automatically select the right openFPGALoader 2023-08-16 15:49:44 -04:00
Adam Mooers 2a97f0a197 Fixed line which combined two git commands 2023-08-15 21:11:20 -04:00
Adam Mooers 37c734f7be Fixed a typo in the top-level README 2023-08-15 17:59:14 -04:00
Adam Mooers f41ab72483 Added relative links to documentation 2023-08-15 17:58:03 -04:00
Adam Mooers 7ef5803cd3 Migrated changes from the upsilon-docker repo to this repo 2023-08-15 17:32:25 -04:00
Adam Mooers 5be3459332 Moved network from to 192.168.2 because 192.168.1 is very common 2023-08-08 23:59:34 -04:00
Adam Mooers 3d00a65147 Revert "Removed docker readme because it is maintained in upsilon-docker repo"
This reverts commit 9f2ad01907.
2023-08-08 23:56:01 -04:00
Adam Mooers 9f2ad01907 Removed docker readme because it is maintained in upsilon-docker repo 2023-08-08 23:44:41 -04:00
Adam Mooers dad7e356fb Moved network from to 192.168.2 because 192.168.1 is very common 2023-08-08 23:41:28 -04:00
Adam Mooers 1243542729 Fixed spacing in assignment 2023-08-08 17:06:36 -04:00
Adam Mooers e6d88df57a csr_bitdwidth.json appears to have been superceded by mmio_descr.py 2023-08-08 17:05:47 -04:00
Adam Mooers 61f1d212b6 Fixed .gitignore to refer to gateware instead of firmware 2023-08-07 23:50:10 -04:00
Adam Mooers de2f3afd1f Removed reference to non-existent file 2023-08-07 23:49:18 -04:00
moose 1595b1cbc0 Fixed path to docker set guide 2023-08-02 22:20:32 -04:00
Peter McGoron cf95a0fd20 refactor compiles 2023-06-28 18:49:26 -04:00
Peter McGoron 054609a459 refactor control loop interface 2023-06-28 17:38:41 -04:00
Peter McGoron 8b8e14bc7f z output reading 2023-06-27 17:50:55 -04:00
Peter McGoron 1a97dfa5aa patch control loop math to newdac widths 2023-06-27 16:01:04 -04:00
Peter McGoron 291329b49e move organization.md to README.md 2023-06-27 13:24:26 -04:00
Peter McGoron 130e1775ac refactor csr2mp and docker Makefile 2023-06-26 15:49:20 -04:00
Peter McGoron f30f6f1ad5 zero scan and documentation 2023-06-23 18:15:53 -04:00
Peter McGoron 2b698fc08a rewrite pins 2023-06-23 14:51:35 -04:00
Peter McGoron addd660bf2 todo.md 2023-06-22 17:18:38 -04:00