upsilon/firmware
Peter McGoron 0a9125355f disable test clock by default 2023-05-11 15:31:52 -04:00
..
rtl disable test clock by default 2023-05-11 15:31:52 -04:00
A7-constraints.xdc cleanup 2022-07-12 13:30:28 -04:00
COPYING COPYING: add A7-constraints.xdc 2023-04-08 16:40:16 +00:00
Makefile update boothmul properly; add clean to make; hardware notes 2023-05-11 14:37:32 -04:00
generate_csr_locations.py fix compile errors 2023-04-18 15:47:57 -04:00
soc.py update boothmul properly; add clean to make; hardware notes 2023-05-11 14:37:32 -04:00